Array substrate for liquid crystal display device and method of fabricating the same

1. An array substrate for a liquid crystal display device, comprising:

a gate line and a data line on a substrate, the data line crossing the gate line to define a pixel region;

an insulating layer between the gate line and the data line;

a switching element adjacent to a crossing of the gate line and the data line;

a pixel electrode connected to the switching element, the pixel electrode disposed in the pixel region;

a first buffer pattern at a first side of the gate line and overlapped with the date line, the first buffer pattern being disposed at the same layer as the gate line,

wherein the first buffer pattern has a bar shape parallel to and is spaced apart from the gate line,

wherein an overlapped portion between the first buffer pattern and the data line has bilateral symmetry, and wherein the first buffer pattern is spaced apart from the pixel electrode in a horizontal plane; and

a second buffer pattern at a second side of the gate line opposite to the first side and overlapped with the data line,

wherein the second buffer pattern extends from the gate line.

2. The array substrate according to claim 1 , wherein the first and second buffer patterns are disposed at the same layer as the gate line.

3. The array substrate according to claim 1 , wherein the second buffer pattern is closer than the first buffer pattern to the switching element.

4. The array substrate according to claim 1 , wherein the second buffer pattern has one of a tetragonal shape and a triangular shape.

5. The array substrate according to claim 2 , wherein the first and second buffer patterns and the gate line are substantially coplanar.

6. The array substrate according to claim 2 , wherein the first and second buffer patterns and the gate line are made of substantially the same material.

7. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate line, a first buffer pattern and a second buffer pattern on a substrate, the first buffer pattern being formed at a first side of the gate line, and the second buffer pattern being formed at a second side of the gate line opposite to the first side,

wherein the first buffer pattern has a bar shape parallel to and is spaced apart from the gate line and

wherein the second buffer pattern extends from the gate line;

forming an insulating layer on the gate line, the first buffer pattern and the second buffer pattern;

forming a date line on the insulating layer, the date line crossing the gate line to define a pixel region, the date line being overlapped with the first buffer pattern and second buffer pattern,

wherein an overlapped portion between the first buffer pattern and the data line has bilateral symmetry;

forming a switching element connected to the gate line and the data line adjacent to a crossing of the gate line and the data line; and

forming a pixel electrode connected to the switching element, the pixel electrode being disposed in the pixel region, wherein the first buffer pattern is spaced apart from the pixel electrode in a horizontal plane.

8. The method according to claim 7 , wherein the steps of forming the gate line, the first buffer pattern and the second buffer pattern include forming the second buffer pattern to have one of a tetragonal shape and a triangular shape.

9. The method according to claim 7 , wherein the steps of forming the gate line, the first buffer pattern and the second buffer pattern include forming the first and second buffer patterns and the gate line to be substantially coplanar.

10. The method according to claim 7 , wherein the steps of forming the gate line, the first buffer pattern and the second buffer pattern include forming the first and second buffer patterns and the gate line of substantially the same material.