Organic light emitting diode display and method of fabricating the same
View Patent ↗An organic light emitting diode display may have a power supply line that is coplanar with a first pixel electrode of an organic light emitting element. The power supply line, first source and drain electrodes of a first thin film transistor (TFT), second source and drain electrodes of a second TFT, a data line, and an upper electrode of a storage capacitor constitute source/drain wire lines. In addition to the power supply line, any one(s) of or all of the source/drain wire lines may be coplanar with the first pixel electrode.
1. An organic light emitting diode display, comprising:
a pixel driving circuit including a first TFT, a second TFT, and a storage capacitor;
an organic light emitting element including a first pixel electrode, a second pixel electrode on the first pixel electrode, and an organic layer between the first and the second electrode, the organic light emitting element being on the pixel driving circuit; and
a power supply line that is coplanar with the first pixel electrode;
wherein the power supply line is integral with a second source electrode of the second TFT and is coupled to an upper electrode of the storage capacitor.
2. The organic light emitting diode display as claimed in claim 1 , wherein the first pixel electrode includes Ag.
3. The organic light emitting diode display as claimed in claim 2 , wherein the first pixel electrode includes ITO/Ag/ITO.
4. The organic light emitting diode display as claimed in claim 1 , wherein second source and drain electrodes of the second TFT and the power supply line are coplanar.
5. The organic light emitting diode display as claimed in claim 4 ,
wherein the upper electrode of the storage capacitor is formed on a layer underneath the power supply line, and
wherein the first pixel electrode is integral with the drain electrode of the second TFT.
6. The organic light emitting diode display as claimed in claim 5 , wherein the first pixel electrode and the power supply line are formed on a planarization layer.
7. The organic light emitting diode display as claimed in claim 5 , wherein the first pixel electrode, the power supply line, and the second source and drain electrodes of the second TFT are formed on a planarization layer.
8. The organic light emitting diode display as claimed in claim 5 , wherein first source and drain electrodes of the first TFT, a data line, the power supply line, and the second source and drain electrodes of the second TFT are coplanar.
9. The organic light emitting diode display as claimed in claim 8 , wherein the first source electrode of the first TFT and the data line are integral.
10. The organic light emitting diode display as claimed in claim 9 , wherein the first source and drain electrodes of the first TFT, the data line, the power supply line, and the second source and drain electrodes of the second TFT are formed on a planarization layer.
11. The organic light emitting diode display as claimed in claim 4 , wherein first source and drain electrodes of the first TFT, a data line, the power supply line, the second source and drain electrodes of the second TFT, and the upper electrode of the storage capacitor are coplanar.
12. The organic light emitting diode display as claimed in claim 11 ,
wherein the power supply line is integral with the second source electrode of the second TFT and the upper electrode of the storage capacitor,
wherein the first pixel electrode is integral with the second drain electrode of the second TFT, and
wherein the first source electrode of the first TFT is integral with the data line.
13. The organic light emitting diode display as claimed in claim 12 , wherein the first source and drain electrodes of the first TFT, the data line, the power supply line, the second source and drain electrodes of the second TFT, and the upper electrode of the storage capacitor are formed on a planarization layer.
14. A method of fabricating an organic light emitting diode display, the method comprising:
forming first and second semiconductor layers of first and second TFTs, respectively, on a sub-pixel region of a substrate;
forming a gate insulating layer;
forming a first gate electrode of the first TFT, a scan line connected to the first gate electrode, a second gate electrode of the second TFT, and a lower electrode of a storage capacitor connected to the second gate electrode;
forming an interlayer insulating film;
forming an upper electrode of the storage capacitor;
forming a data line;
forming first source and drain electrodes of the first TFT;
forming second source and drain electrodes of the second TFT;
forming a power supply line coupled to the second source electrode and the upper electrode of the storage capacitor;
forming a first pixel electrode coupled to the second drain electrode, the first pixel electrode being coplanar with the power supply line; and
sequentially stacking an organic layer and a second pixel electrode on the first pixel electrode;
wherein forming the power supply line includes integrating the power supply line and the second source electrode of the second TFT.
15. The method as claimed in claim 14 , wherein, before forming the power supply line and the first pixel electrode, forming a planarization layer.
16. The method as claimed in claim 15 , wherein forming the planarization layer is performed after at least one of forming the interlayer insulating film, the upper electrode of the storage capacitor, the data line, and the first source and drain electrodes of the first TFT.
17. The method as claimed in claim 16 , wherein, after forming the planarization layer, forming the second source and drain electrodes of the second TFT, the second source and drain electrodes of the second TFT being coplanar with the power supply line.
18. The method as claimed in claim 17 , wherein forming the first pixel electrode includes integrating the first pixel electrode and the second drain electrode.
19. The method as claimed in claim 17 , wherein, after forming the planarization layer, forming the first source and drain electrodes of the first TFT, and forming the data line, the first source and drain electrodes of the first TFT and the data line being coplanar with the power supply line.
20. The method as claimed in claim 19 , wherein forming the power supply line includes integrating the power supply line and the second source electrode, forming the first pixel electrode includes integrating the first pixel electrode and the second drain electrode, and forming the first source electrode includes integrating the first source electrode and the data line.
21. The method as claimed in claim 19 , wherein, after forming the planarization layer, forming the upper electrode of the storage capacitor, the upper electrode of the storage capacitor being coplanar with the power supply line.
22. The method as claimed in claim 21 , wherein forming the power supply line includes integrating the power supply line, the second source electrode and the upper electrode of the storage capacitor, forming the first pixel electrode includes integrating the first pixel electrode and the second drain electrode, and forming the first source electrode includes integrating the first source electrode and the data line.
23. An organic light emitting diode display, comprising:
a pixel driving circuit including a first TFT, a second TFT, and a storage capacitor;
an organic light emitting element including a first pixel electrode, a second pixel electrode on the first pixel electrode, and an organic layer between the first and the second electrode, the organic light emitting element being on the pixel driving circuit; and
a power supply line that is coplanar with and made of a same material as the first pixel electrode.