Method for fabricating high voltage semiconductor device
View Patent ↗A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising: forming a mask pattern on the semiconductor substrate; forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode; selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask; and forming the gate insulating layer and the gate electrode using the gate-formation mask.
1. A method for fabricating a high voltage semiconductor device, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising:
forming a mask pattern on the semiconductor substrate;
forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode;
selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask;
forming the gate insulating layer and the gate electrode using the gate formation mask;
removing the gate-formation mask after the gate electrode is formed; and
forming a second low-density impurity implanted region on the semiconductor substrate so that the second low-density impurity implanted region is located outside the first low-density impurity implanted region.
2. A method for fabricating a high voltage semiconductor device according to claim 1 , wherein the mask pattern and the gate-formation mask are made of an oxide layer.
3. A method for fabricating a high voltage semiconductor device according to claim 1 , wherein
the first low-density impurity implanted region is formed by implanting phosphorus.
4. A method for fabricating a high voltage semiconductor device according to claim 3 ,
forming a high-density impurity implanted region after the second low-density impurity-implanted region is formed, the high-density impurity implanted region having a higher density of impurity than the first and second low-density impurity-implanted regions.
5. A method for fabricating a high voltage semiconductor device according to claim 1 , further comprising:
forming a side wall on side surfaces of the gate electrode and the gate insulating layer.
6. A method for fabricating a high voltage semiconductor device according to claim 1 , wherein
the step of forming the gate electrode comprises: filling a gate electrode material in a cavity of the gate-formation mask; and polishing an upper portion of the gate electrode material.
7. A method for fabricating a high voltage MOS transistor, which comprises a semiconductor substrate; a gate insulation layer formed on the semiconductor substrate; and a gate electrode formed on the gate insulation layer, comprising:
forming a mask pattern on the semiconductor substrate;
forming a first low-density impurity implanted region on the semiconductor substrate using the mask pattern, in which the first low-density impurity implanted region is overlapped with the gate electrode;
selectively removing a part of the mask pattern from a region where the gate electrode is to be formed to form a gate-formation mask;
forming the gate insulating layer and the gate electrode using the gate-formation mask;
removing the gate-formation mask after the gate electrode is formed;
forming a second low-density impurity implanted region on the semiconductor substrate so that the second low-density impurity implanted region is located outside the first low-density impurity implanted region; and
forming a high-density impurity implanted region after the second low-density impurity-implanted region is formed, the high-density impurity implanted region having a higher density of impurity than the first and second low-density impurity-implanted regions.
8. A method for fabricating a high voltage MOS transistor according to claim 7 , wherein
the first and second low-density impurity implanted regions are formed by implanting phosphorus.
9. A method for fabricating a high voltage MOS transistor according to claim 7 , further comprising:
forming a side wall on side surfaces of the gate electrode and the gate insulating layer.
10. A method for fabricating a high voltage MOS transistor according to claim 7 , wherein
the mask pattern and the gate-formation mask is made of an oxide layer.
11. A method for fabricating a high voltage MOS transistor according to claim 7 , wherein
the step of forming the gate electrode comprises: filling a gate electrode material in a cavity of the gate-formation mask; and polishing an upper portion of the gate electrode material.