Electron blocking layers for electronic devices
Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.
1 . A memory device, comprising:
a substrate;
a source region of the substrate;
a drain region of the substrate;
a channel region between the source region and drain region;
a tunneling dielectric layer over the substrate adjacent to the channel region;
a charge storage layer over the tunneling dielectric layer;
a charge blocking layer over the charge storage layer;
a control dielectric layer over the charge blocking layer; and
a control gate over the control dielectric layer.
2 . The memory device of claim 1 , wherein the charge storage layer comprises at least one of physical vapor deposition (PVD) dots, chemical vapor deposition (CVD) dots, or colloidal dots.
3 . The memory device of claim 1 , wherein the charge storage layer is a continuous metal or semiconducting layer.
4 . The memory device of claim 1 , wherein the charge storage layer is a non-contiguous metal or semiconducting layer.
5 . The memory device of claim 1 , wherein the charge storage layer comprises a plurality of nanoparticles.
6 . The memory device of claim 1 , wherein the charge storage layer comprises a nitride layer.
7 . The memory device of claim 5 , wherein the nanoparticles are nanocrystals.
8 . The memory device of claim 1 , wherein said tunneling dielectric layer comprises an oxide.
9 . The memory device of claim 1 , wherein the control dielectric layer is Al 2 O 3 .
10 . The memory device of claim 1 , further comprising:
a barrier layer between the tunneling dielectric layer and the charge storage layer.
11 . The memory device of claim 10 , wherein the barrier layer comprises nitrogen.
12 . The memory device of claim 1 , wherein the charge blocking layer comprises HfO 2 .
13 . The memory device of claim 1 , wherein the charge blocking layer comprises at least one of Al 2 O 3 , SiO 2 , or HfAlO 3 .
14 . The memory device of claim 1 , wherein the charge blocking layer is a high-k dielectric material.
15 . The memory device of claim 1 , wherein the charge blocking layer includes at least one of Gd 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Y 2 O 3 , La 2 O 3 , ZrO 2 , TiO 2 , Ta 2 O 5 , SrTiO 3 , BaxSr1-xTiO 3 , ZrxSi1-xOy, HfxSi1-xOy, AlxZr1-xO 2 , or Pr 2 O.
16 . The memory device of claim 1 , wherein the charge blocking layer is formed as a gradient of material
17 . The memory device of claim 1 , wherein the charge blocking layer comprises a plurality of layers.
18 . The memory device of claim 17 , wherein the plurality of layers includes a first layer that is directly adjacent to the charge storage layer, wherein the first layer comprises a material having a higher band gap than a band gap of a material of a second layer of the plurality of layers.
19 . The memory device of claim 1 , wherein the charge blocking layer is doped with a dopant material.
20 . The memory device of claim 19 , wherein the dopant material is a rare earth metal or silicate.
21 . The memory device of claim 1 , wherein the charge blocking layer has a thickness less than about 4 nm.
22 . The memory device of claim 1 , wherein the charge blocking layer has a thickness less than about 2 nm.
23 . The memory device of claim 1 , wherein the charge blocking layer has a higher dielectric constant than the control dielectric layer.
24 . The memory device of claim 1 , further comprising:
a second charge blocking layer between the control dielectric layer and the control gate.
25 . The memory device of claim 24 , wherein the second charge blocking layer comprises HfO 2 .
26 . The memory device of claim 24 , wherein the second charge blocking layer comprises at least one of Al 2 O 3 , SiO 2 , or HfAlO 3 .
27 . The memory device of claim 24 , wherein the second charge blocking layer is a high-k dielectric material.
28 . The memory device of claim 24 , wherein the second charge blocking layer includes at least one of Gd 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Y 2 O 3 , La 2 O 3 , ZrO 2 , TiO 2 , Ta 2 O 5 , SrTiO 3 , BaxSr1-xTiO 3 , ZrxSi1-xOy, HfxSi1-xOy, AlxZr1-xO 2 , or Pr 2 O.
29 . The memory device of claim 24 , wherein the second charge blocking layer is formed as a gradient of material
30 . The memory device of claim 24 , wherein the second charge blocking layer comprises a plurality of layers.
31 . The memory device of claim 30 , wherein the plurality of layers includes a first layer that is directly adjacent to the control dielectric layer, wherein the first layer comprises a material having a higher band gap than a band gap of a material of a second layer of the plurality of layers.
32 . The memory device of claim 24 , wherein the second charge blocking layer is doped with a dopant material.
33 . The memory device of claim 32 , wherein the dopant material is a rare earth metal or silicate.
34 . The memory device of claim 24 , wherein the second charge blocking layer has a thickness less than about 4 nm.
35 . The memory device of claim 24 , wherein the second charge blocking layer has a thickness less than about 2 nm.
36 . The memory device of claim 24 , wherein the second charge blocking layer has a higher dielectric constant than the control dielectric layer.
37 . The memory device of claim 24 , wherein the memory device has a program/erase window of greater than about 9 volts.
38 . The memory device of claim 37 , wherein the program/erase window is greater than about 10 volts.
39 . The memory device of claim 38 , wherein the program/erase window is greater than about 11 volts.
40 . The memory device of claim 39 , wherein the program/erase window is greater than about 12 volts.
41 . The memory device of claim 1 , wherein the memory device is a non-volatile memory device.
42 . The memory device of claim 1 , wherein the memory device is a flash memory device.
43 . A gate stack of a memory device, comprising:
a tunneling dielectric layer over a substrate of the memory device;
a charge storage layer over the tunneling dielectric layer;
a charge blocking layer over the charge storage layer; and
a control dielectric layer over the first charge blocking layer;
wherein a control gate is over the control dielectric layer.
44 . The gate stack of claim 43 , wherein the charge storage layer comprises at least one of physical vapor deposition (PVD) dots, chemical vapor deposition (CVD) dots, or colloidal dots.
45 . The gate stack of claim 43 , wherein the charge storage layer is a continuous metal or semiconducting layer.
46 . The gate stack of claim 43 , wherein the charge storage layer is a non-contiguous metal or semiconducting layer.
47 . The gate stack of claim 43 , wherein the charge storage layer comprises a plurality of nanoparticles.
48 . The gate stack of claim 47 , wherein the nanoparticles are nanocrystals.
49 . The gate stack of claim 43 , wherein the charge storage layer comprises a nitride layer.
50 . The gate stack of claim 43 , wherein said tunneling dielectric layer comprises an oxide.
51 . The gate stack of claim 43 , wherein the control dielectric layer is Al 2 O 3 .
52 . The gate stack of claim 43 , further comprising:
a barrier layer between the tunneling dielectric layer and the charge storage layer.
53 . The gate stack of claim 52 , wherein the barrier layer comprises nitrogen.
54 . The gate stack of claim 43 , wherein the charge blocking layer comprises HfO 2 .
55 . The gate stack of claim 43 , wherein the charge blocking layer comprises at least one of Al 2 O 3 , SiO 2 , or HfAlO 3 .
56 . The gate stack of claim 43 , wherein the charge blocking layer is a high-k dielectric material.
57 . The gate stack of claim 43 , wherein the charge blocking layer includes at least one of HfAlO 3 , Gd 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Y 2 O 3 , La 2 O 3 , ZrO 2 , TiO 2 , Ta 2 O 5 , SrTiO 3 , BaxSr1-xTiO 3 , ZrxSi1-xOy, HfxSi1-xOy, AlxZr1-xO 2 , or Pr 2 O.
58 . The gate stack of claim 43 , wherein the charge blocking layer is formed as a gradient of material
59 . The gate stack of claim 43 , wherein the charge blocking layer comprises a plurality of layers.
60 . The gate stack of claim 59 , wherein the plurality of layers includes a first layer that is directly adjacent to the charge storage layer, wherein the first layer comprises a material having a higher band gap than a band gap of a material of a second layer of the plurality of layers.
61 . The gate stack of claim 43 , wherein the charge blocking layer is doped with a dopant material.
62 . The gate stack of claim 61 , wherein the dopant material is a rare earth metal or silicate.
63 . The gate stack of claim 43 , wherein the charge blocking layer has a thickness less than about 4 nm.
64 . The gate stack of claim 43 , wherein the charge blocking layer has a thickness less than about 2 nm.
65 . The gate stack of claim 43 , wherein the charge blocking layer has a higher dielectric constant than the control dielectric layer.
66 . The gate stack of claim 43 , further comprising:
a second charge blocking layer between the control dielectric layer and the control gate.
67 . The gate stack of claim 66 , wherein the second charge blocking layer comprises HfO 2 .
68 . The gate stack of claim 66 , wherein the second charge blocking layer comprises at least one of Al 2 O 3 , SiO 2 , or HfAlO 3 .
69 . The gate stack of claim 66 , wherein the second charge blocking layer is a high-k dielectric material.
70 . The gate stack of claim 66 , wherein the second charge blocking layer includes at least one of HfAlO 3 , Gd 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Y 2 O 3 , La 2 O 3 , ZrO 2 , TiO 2 , Ta 2 O 5 , SrTiO 3 , BaxSr1-xTiO 3 , ZrxSi1-xOy, HfxSi1-xOy, AlxZr1-xO 2 , or Pr 2 O.
71 . The gate stack of claim 66 , wherein the second charge blocking layer is formed as a gradient of material
72 . The gate stack of claim 66 , wherein the second charge blocking layer comprises a plurality of layers.
73 . The gate stack of claim 72 , wherein the plurality of layers includes a first layer that is directly adjacent to the control dielectric layer, wherein the first layer comprises a material having a higher band gap than a band gap of a material of a second layer of the plurality of layers.
74 . The gate stack of claim 66 , wherein the second charge blocking layer is doped with a dopant material.
75 . The gate stack of claim 74 , wherein the dopant material is a rare earth metal or silicate.
76 . The gate stack of claim 66 , wherein the second charge blocking layer has a thickness less than about 4 nm.
77 . The gate stack of claim 66 , wherein the second charge blocking layer has a thickness less than about 2 nm.
78 . The gate stack of claim 66 , wherein the second charge blocking layer has a higher dielectric constant than the control dielectric layer.
79 . The gate stack of claim 66 , wherein the memory device has a program/erase window of greater than about 9 volts.
80 . The gate stack of claim 79 , wherein the program/erase window is greater than about 10 volts.
81 . The gate stack of claim 80 , wherein the program/erase window is greater than about 11 volts.
82 . The gate stack of claim 81 , wherein the program/erase window is greater than about 12 volts.
83 . The gate stack of claim 43 , wherein the memory device is a non-volatile memory device.
84 . The gate stack of claim 43 , wherein the memory device is a flash memory device.
85 . A method for forming a memory device, comprising:
forming a tunneling dielectric layer over a substrate;
forming a charge storage layer over the tunneling dielectric layer;
forming a charge blocking layer over the charge storage layer;
forming a control dielectric layer over the charge blocking layer; and
forming a control gate over the control dielectric layer.
86 . The method of claim 85 , further comprising:
forming a source region of the substrate; and
forming a drain region of the substrate.
87 . The method of claim 85 , wherein the charge storage layer comprises quantum dots, further comprising:
forming the dots according to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a colloidal dot process.
88 . The method of claim 85 , wherein said step of forming the charge storage layer comprises:
forming the charge storage layer as a continuous metal or semiconducting layer.
89 . The method of claim 85 , wherein said step of forming the charge storage layer comprises:
forming the charge storage layer as a non-contiguous metal or semiconducting layer.
90 . The method of claim 85 , wherein said step of forming the charge storage layer comprises:
forming a plurality of nanoparticles over the tunneling dielectric layer.
91 . The method of claim 90 , wherein the nanoparticles are nanocrystals.
92 . The method of claim 85 , wherein said step of forming the charge storage layer comprises:
forming the charge storage layer as a nitride layer.
93 . The method of claim 85 , wherein said step of forming the tunneling dielectric layer comprises:
oxidizing a surface of the substrate.
94 . The method of claim 85 , wherein said step of forming the control dielectric layer comprises:
forming a layer of Al 2 O 3 over the charge blocking layer.
95 . The method of claim 85 , further comprising:
forming a barrier layer between the tunneling dielectric layer and the charge storage layer.
96 . The method of claim 95 , wherein said step of forming the barrier layer comprises:
depositing nitrogen or a nitrogen-containing compound to the tunneling dielectric layer using a chemical vapor deposition (CVD) process.
97 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming a layer of HfO 2 over the charge storage layer.
98 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming a layer of at least one of Al 2 O 3 , SiO 2 , or HfAlO 3 over the charge storage layer.
99 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming a layer of a high-k dielectric material over the charge storage layer.
100 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming a layer of at least one of HfAlO 3 , Gd 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Y 2 O 3 , La 2 O 3 , ZrO 2 , TiO 2 , Ta 2 O 5 , SrTiO 3 , BaxSr1-xTiO 3 , ZrxSi1-xOy, HfxSi1-xOy, AlxZr1-xO 2 , or Pr 2 O over the charge storage layer.
101 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming a material over the charge storage layer as a gradient.
102 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming a plurality of layers of dielectric material over the charge storage layer.
103 . The method of claim 102 , wherein said step of forming a plurality of layers comprises:
forming a first layer of the plurality of layers includes directly adjacent to the charge storage layer, the first layer comprising a material having a higher band gap than a band gap of a material of a second layer of the plurality of layers.
104 . The method of claim 85 , further comprising:
doping the charge blocking layer with a dopant material.
105 . The method of claim 104 , wherein said step of doping the charge blocking layer comprises:
doping the charge blocking layer with a rare earth metal or silicate.
106 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming the charge blocking layer to have a thickness less than about 4 nm.
107 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming the charge blocking layer to have a thickness less than about 2 nm.
108 . The method of claim 85 , wherein said step of forming the charge blocking layer comprises:
forming the charge blocking layer from a material that has a higher dielectric constant than a material of the control dielectric layer.
109 . The method of claim 85 , further comprising:
forming a second charge blocking layer over the control dielectric layer to be positioned between the control dielectric layer and the control gate.
110 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming a layer of HfO 2 over the control dielectric layer.
111 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming a layer of at least one of Al 2 O 3 , SiO 2 , or HfAlO 3 over the control dielectric layer.
112 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming a layer of a high-k dielectric material over the control dielectric layer.
113 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming a layer of at least one of HfAlO 3 , Gd 2 O 3 , Yb 2 O 3 , Dy 2 O 3 , Nb 2 O 5 , Y 2 O 3 , La 2 O 3 , ZrO 2 , TiO 2 , Ta 2 O 5 , SrTiO 3 , BaxSr1-xTiO 3 , ZrxSi1-xOy, HfxSi1-xOy, AlxZr1-xO 2 , or Pr 2 O over the control dielectric layer.
114 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming a material over the control dielectric layer as a gradient.
115 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming a plurality of layers of dielectric material over the control dielectric layer.
116 . The method of claim 115 , wherein said step of forming a plurality of layers comprises:
forming a first layer of the plurality of layers includes directly adjacent to the control dielectric layer, the first layer comprising a material having a higher band gap than a band gap of a material of a second layer of the plurality of layers.
117 . The method of claim 109 , further comprising:
doping the charge blocking layer with a dopant material.
118 . The method of claim 117 , wherein said step of doping the second charge blocking layer comprises:
doping the second charge blocking layer with a rare earth metal or silicate.
119 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming the second charge blocking layer to have a thickness less than about 4 nm.
120 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming the second charge blocking layer to have a thickness less than about 2 nm.
121 . The method of claim 109 , wherein said step of forming the second charge blocking layer comprises:
forming the second charge blocking layer from a material that has a higher dielectric constant than a material of the control dielectric layer.
122 . The method of claim 109 , wherein the memory device has a program/erase window of greater than about 9 volts.
123 . The method of claim 122 , wherein the program/erase window is greater than about 10 volts.
124 . The method of claim 123 , wherein the program/erase window is greater than about 11 volts.
125 . The method of claim 124 , wherein the program/erase window is greater than about 12 volts.
126 . The method of claim 85 , wherein the memory device is a non-volatile memory device.
127 . The method of claim 85 , wherein the memory device is a flash memory device.
128 . The method of claim 85 , further comprising:
configuring the memory device as a multi-state memory device.
129 . A flash memory device, comprising:
a memory cell having a program/erase window of greater than about 9 volts.
130 . The flash memory device of claim 129 , wherein the program/erase window is greater than about 10 volts.
131 . The flash memory device of claim 130 , wherein the program/erase window is greater than about 11 volts.
132 . The flash memory device of claim 131 , wherein the program/erase window is greater than about 12 volts.
133 . The flash memory device of claim 129 , wherein the memory cell comprises a charge storage layer;
wherein the charge storage layer comprises quantum dots formed according to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or a colloidal dot process.