Memory controller
Reference number 21 indicates a CPU, reference number 22 indicates a memory controller, and reference number 23 indicates a parameter set register group that has access parameters shared and used by banks. In the parameter set register group 23 , parameter sets S 0 to Sn having elements P 0 to Pn exist. Reference number 24 indicates an external memory group to be finally accessed. A parameter set selection register 27 selects a parameter set among the parameter sets S 0 to Sn of the parameter set register group 23 so as to be corresponded to each bank. The parameter set selection register 27 stores a unique identifier for each of banks B 0 to Bm, which select the parameter sets S 0 to Sn.
1 . A memory controller that divides a memory space to be accessed by a CPU into a plurality of banks and accesses each bank on the basis of an access mode determined by a parameter set corresponding to each bank, the memory controller comprising:
a register that selects a parameter set corresponding to each bank from a parameter set register which stores the parameter set in the form of a table capable of being commonly used in each bank, and sets an access mode for each bank.
2 . The memory controller according to claim 1 ,
wherein the register stores an identifier of the parameter set corresponding to each bank.
3 . The memory controller according to claim 2 ,
wherein the register is set in a non-defined area in the memory space.
4 . The memory controller according to claim 1 ,
wherein the number of parameter sets are smaller than the number of banks.
5 . The memory controller according to claim 4 ,
wherein an initial value is the parameter set corresponding to a low speed mode.
6 . The memory controller according to claim 1 , further comprising:
a ROM that stores a parameter set of which utilization is estimated in advance.
7 . The memory controller according to claim 1 , further comprising:
a bandwidth detecting circuit that detects an access frequency of the CPU to the bank and selects the parameter set on the basis of the access frequency.
8 . The memory controller according to claim 1 , further comprising:
a bandwidth detecting circuit that detects an access frequency of the CPU to the bank and changes a set value of the parameter set selection register on the basis of the access frequency.
9 . The memory controller according to claim 1 , further comprising:
a power saving mode control circuit that, in a power saving mode, selects an access mode corresponding to the power saving mode.
10 . The memory controller according to claim 1 , further comprising:
an access mode sequencer that holds a sequence for switching an access mode to the bank in accordance with a predetermined event.
11 . The memory controller according to claim 10 , further comprising:
an event trigger register that detects an event and informs the access mode sequencer of timing for switching the bank.