Input/output logical circuit
View Patent ↗A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
1. A semiconductor chip comprising:
a first unit coupled to receive at least a first input clock signal and a second input clock signal, and output a first output clock signal;
a second unit coupled to receive the first input clock signal and the second input clock signal, and output a second output clock signal that has periodically the first logic level and the second logic level;
a first transfer gate which receives a first data, and transmits the first data to a data bus in response to a first logic level of the first output clock signal;
a second transfer gate which receives a second data, and transmits the second data to the data bus in response to the first logic level of the second output clock signal;
wherein the first unit changes the first output clock signal from a second logic level to the first logic level when a change of the first input clock signal from the second logic level to the first logic level is detected, and the second unit changes the second output clock signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
2. A semiconductor chip according to claim 1 , wherein the first input clock signal, the second input clock signal and the first output clock signal have periodically a first logic level or a second logic level and a period of the first logic level of the second output clock signal does not overlap a period of the first logic level of the first output clock signal.
3. A semiconductor chip according to claim 1 , wherein the first input clock signal and the second input clock signal have mutually shifted phases.
4. A semiconductor chip according to claim 1 , wherein the first data and the second data are alternately outputted in serial.
5. A semiconductor chip according to claim 4 , further comprising:
a latch circuit that latches one of the first data and the second data.
6. A semiconductor chip according to claim 1 , wherein the first input clock signal and the second input clock signal are supplied from a DLL Delay Circuit.
7. A semiconductor chip according to claim 1 , wherein a period of the first logic level of the first input clock signal partially overlaps with that of the first logic level of the first input clock.
8. A semiconductor chip according to claim 1 , wherein the second unit changes the second output clock signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal and when the first logic level of the first input clock signal is detected at a time of detection of the change of the second input clock signal from the second logic level to the first logic level.
9. A semiconductor chip comprising:
a first unit coupled to receive a first input clock signal and a second input clock signal and output a first output clock signal;
a second unit coupled to receive the first input clock signal and the second input clock signal and output a second output clock signal;
a circuit coupled to receives a first data and a second data and outputs the first data and the second data in serial in response to the first output signal and the second output signal, the circuit is arranged wired-or connection;
wherein the first unit changes the first output clock signal from the second logic level to the first logic level when a change of the first input clock signal from the second logic level to the first logic level is detected, and the second unit changes the second output clock signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
10. A semiconductor chip according to claim 9 , wherein the first input clock signal and the second input clock signal are supplied from a DLL Delay Circuit.
11. A semiconductor chip according to claim 10 , wherein a period of the first logic level of the first input clock signal partially overlaps with that of the first logic level of the first input clock.
12. A semiconductor chip according to claim 9 , wherein the second unit changes the second output clock signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal and when the first logic level of the first input clock signal is detected at a time of detection of the change of the second input clock signal from the second logic level to the first logical logic level.