Method for selective epitaxial growth of source/drain areas

1. A method of performing selective epitaxial growth of source/drain (S/D) areas, comprising:

providing a substrate of a semiconductor material, the substrate comprising a first substrate area and a second substrate area, the first area comprising at least one gate stack;

applying at least a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate;

removing the poly-Si or poly-SiGe top layer from the first area of the substrate selectively towards the poly-Si or poly-SiGe top layer in the second substrate area;

removing simultaneously the poly-Si or poly-SiGe top layer on the second substrate area and at least a part of the substrate in the S/D areas of the first substrate area selectively toward the at least one gate stack; and

performing a selective epitaxial growth of S/D areas in the first substrate area.

Wherein between the poly-Si or poly-SiGe top layer and the substrate a stop layer is applied, which is not etchable with the same etch chemistry as the top layer;

wherein the removing of the poly-Si or poly-SiGe top layer from the first area is performed until the stop layer is exposed;

wherein the simultaneously removing comprises a breakthrough etch process for removing the stop layer.

2. The method of claim 1 , further comprising depositing and patterning a resist layer on top of the poly-Si or poly-SiGe top layer in order to mask the second area and expose the first area.

3. The method of claim 2 , further comprising removing resist on top of the second area, between the process of removing the poly-Si or poly-SiGe top layer from the first area and the process of simultaneously removing.

4. The method of claim 1 , wherein the second area comprises at least one gate stack.

5. The method of claim 1 , further comprising end-point triggering.

6. The method of claim 1 , wherein the substrate is formed of silicon, germanium or SiGe.

7. The method of claim 1 , wherein the substrate and the poly-Si top layer are etched with a mixture of SF6 and HBr.

8. The method of claim 1 , wherein the poly-Si or poly-SiGe top layer has a thickness approximately between 20-150 nm.

9. The method of claim 1 , wherein the poly-SiGe top layer has a Ge concentration approximately between 0% to 0.5%.

10. The method of claim 1 , wherein the stop layer is formed of Si oxide.

11. The method of claim 10 , wherein the Si oxide stop layer has a thickness approximately between 0-30 nm.