IP Library Granted Patent US 7,602,236
Granted Patent B2
US 7,602,236 · App. 11/645,530 · Granted Oct 13, 2009

Band gap reference voltage generation circuit

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Quick Facts
Patent No.
US 7,602,236
App. No.
11/645,530
Granted
Oct 13, 2009
Kind
B2
Abstract

There is provided a band gap reference voltage generation circuit capable of reducing wake up time during transition from an idle mode to a normal mode and further capable of removing the RF noise of an output voltage. The band gap reference voltage generation circuit includes an operation amplifier for outputting a uniform voltage in accordance with a reference voltage input to an inversion terminal and a non-inversion terminal; a first-type first transistor for outputting a power source voltage in accordance a power down signal; a first-type second transistor for outputting bias current corresponding to an output voltage from the operation amplifier using an output voltage from the first-type first transistor; a reference voltage circuit for supplying a reference voltage to the inversion terminal and the non-inversion terminal using the bias current; a second-type first transistor different from the first-type first transistor for supplying a base voltage to the output port of the operation amplifier in accordance with the power down signal; a start up circuit for driving the entire circuit during power up; a first node between the second-type second transistor and the reference voltage circuit; and an output terminal connected to the first node.

Claims (26)

1. A band gap reference voltage generation circuit comprising:

an operation amplifier for outputting a uniform voltage in accordance with a reference voltage input to an inversion terminal and a non-inversion terminal;

a first-type first transistor for outputting a power source voltage in accordance with a power down signal;

a first-type second transistor for outputting a bias current corresponding to the uniform voltage in response to the power source voltage from the first-type first transistor;

a reference voltage circuit for supplying a reference voltage to the inversion terminal and the non-inversion terminal in response to the bias current;

a second-type first transistor for supplying a base voltage to an output port of the operation amplifier in accordance with the power down signal;

a start up circuit for driving the bandgap reference circuit during power up;

a first node between the first-type second transistor and the reference voltage circuit;

an output terminal connected to the first node; and

a noise filter circuit connected to the power source voltage, the base voltage, and the first node to remove RF noise of an output voltage of the first node and to output the output voltage of the first node to the output terminal, wherein the noise filter circuit comprises:

a first-type sixth transistor connected between the first node and the output terminal;

a first-type seventh transistor connected between the power source voltage and the output terminal; and

a second-type sixth transistor controlled in accordance with the power down signal and connected between the output terminal and the base voltage; wherein

the first-type sixth transistor functions as a capacitor and includes a gate terminal connected to the base voltage, a source terminal connected to the first node, and a drain terminal connected to the output terminal, and

the first-type seventh transistor functions to provide an impedance and includes a gate terminal connected to the output terminal and source and drain terminals connected to the power source voltage.

2. The band gap reference voltage generation circuit of claim 1 , wherein first-type transistors are p-type, and second-type transistors are n-type.

3. The band gap reference voltage generation circuit of claim 1 , wherein the reference voltage circuit comprises:

a first resistor and a first bipolar transistor serially connected to the first node and the base voltage; and

second and third resistors and a second bipolar transistor serially connected to the first node and the base voltage.

4. The band gap reference voltage generation circuit of claim 3 , wherein the first and second bipolar transistors form current mirrors.

5. The band gap reference voltage generation circuit of claim 1 , wherein the start up circuit comprises:

a first-type third transistor controlled in accordance with the power down signal and connected to the power source voltage;

a first-type fourth transistor whose gate terminal is connected to a drain and a source terminal of the first-type fourth transistor, which is connected to a drain terminal of the first-type third transistor;

second-type second to fourth transistors serially connected to the first-type fourth transistor in the form of diodes;

a first-type fifth transistor for outputting the output voltage of the operation amplifier in accordance with the gate voltage of the second-type second to fourth transistors; and

a second-type fifth transistor controlled in accordance with an inversed power down signal and connected to the first-type fifth transistor and the base voltage.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2015
From: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 035620/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2015
From: DONGBU HITEK CO., LTD.
To: STRATEGIC GLOBAL ADVISORS OF OREGON, INC.
Reel/Frame 035491/0744 →
MERGER Recorded Apr 22, 2015
From: DONGBU ELECTRONICS CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 035469/0801 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2006
From: JO, EUN SANG
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018745/0035 →