Liquid crystal display device and method for driving the same
View Patent ↗A liquid crystal display device including a liquid crystal panel, a gate driver configured to supply gate signals to gate lines on the liquid crystal panel, a data driver configured to supply data voltages to data lines on the liquid crystal panel, and a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines.
1. A liquid crystal display device, comprising:
a liquid crystal panel;
a gate driver configured to supply gate signals to gate lines on the liquid crystal panel;
a data driver configured to supply data voltages to data lines on the liquid crystal panel;
a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines, wherein the partial controller generates a vertical window control signal which controls an output time period of the gate driver, to the gate driver; and
a delay section configured to delay the vertical window control signal supplied to the gate driver from the partial controller by a predetermined time period,
wherein the vertical window control signal has a vertical window pulse of a low logic for designating an output limit period of the gate signal during a time period of a vertical synchronous signal.
2. The liquid crystal display device according to claim 1 , wherein the gate driver includes:
a plurality of shift register stages dependently connected to each other and configured to generate the gate signals; and
a plurality of output switch sections configured to selectively intercept the gate signals to be supplied to corresponding gate lines from the plurality of shift register stages in response to a control of the partial controller.
3. The liquid crystal display device according to claim 2 , wherein the partial controller supplies the vertical window pulse to the plurality of output switch sections in common.
4. The liquid crystal display device according to claim 3 , wherein the plurality of output switch sections intercept the gate signals during the time period of the vertical window pulse.
5. The liquid crystal display device according to claim 1 , wherein the partial controller further controls the data driver to display a part of pixels on the liquid crystal panel corresponding to a remainder of the gate signals with a black color.
6. The liquid crystal display device according to claim 1 , wherein the partial controller further controls the data driver to initialize pixels on the liquid crystal panel corresponding to the part of the gate signals with a black color.
7. The liquid crystal display device according to claim 6 , wherein the partial controller further controls the data driver to display a part of pixels on the liquid crystal panel corresponding to a remainder of the gate signals with a black color.
8. A liquid crystal display device comprising:
a liquid crystal panel;
a gate driver configured to supply gate signals to gate lines on the liquid crystal panel;
a data driver configured to supply data voltages to data lines on the liquid crystal panel;
a timing controller configured to control driving timings of the gate driver and the data driver, and to supply a pixel data stream to the data driver;
a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines, wherein the partial controller generates a vertical window control signal which controls an output time period of the gate driver, to the gate driver; and
a delay section configured to delay the vertical window control signal supplied to the gate driver from the partial controller by a predetermined time period,
wherein the vertical window control signal has a vertical window pulse of a low logic for designating an output limit period of the gate signal during a time period of a vertical synchronous signal.
9. The liquid crystal display device according to claim 8 , wherein the gate driver includes:
a plurality of shift register stages configured to dependently generate the gate signals in response to a gate start pulse from the timing controller; and
a plurality of output switch sections configured to selectively intercept the gate signals to be supplied to corresponding gate lines from the plurality of shift register stages in response to a control of the partial controller.
10. The liquid crystal display device according to claim 9 , wherein the partial controller supplies the vertical window pulse to the plurality of output switch sections in common.
11. The liquid crystal display device according to claim 10 , wherein the plurality of output switch sections intercept the gate signals during the time period of the vertical window pulse.
12. The liquid crystal display device according to claim 8 , wherein the partial controller further controls the timing controller to display a part of pixels on the liquid crystal panel corresponding to a remainder of the gate signals with a black color.
13. The liquid crystal display device according to claim 8 , wherein the partial controller further controls the timing controller to initialize pixels on the liquid crystal panel corresponding to the part of the gate signals with a black color.