Array substrate for liquid crystal display device and method of manufacturing the same
View Patent ↗An array substrate for a liquid crystal display device includes a substrate, a gate line over the substrate, a data line crossing the gate line to define a pixel region and including a transparent conductive layer and an opaque conductive layer, a data pad at one end of the data line and including a transparent conductive layer, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, the pixel electrode including a transparent conductive layer.
1. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line over the substrate;
a data line crossing the gate line to define a pixel region, the data line including a transparent conductive layer and a conductive metallic layer;
a data pad at one end of the data line and including a transparent conductive layer;
a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a source electrode and a drain electrode, wherein each of the source electrode and the drain electrode includes a transparent conductive layer and a conductive metallic layer; and
a pixel electrode in the pixel region and connected to the thin film transistor,
wherein the pixel electrode and the transparent conductive layer of the drain electrode are formed of the same layer and the same material, and
wherein the active layer has an island shape and is disposed over and within the gate electrode.
2. The array substrate according to claim 1 , wherein the thin film transistor includes a buffer metallic layer.
3. The array substrate according to claim 2 , wherein the buffer metallic layer is disposed between the ohmic contact layer and the transparent conductive layer of each of the source and drain electrodes.
4. The array substrate according to claim 1 , further comprising a gate pad and a gate pad electrode, wherein the gate pad is disposed at one end of the gate line and the gate pad electrode contacts the gate pad, the gate pad electrode including a transparent conductive layer.
5. The array substrate according to claim 4 , further comprising an insulating layer covering the gate line, the thin film transistor and the data line and exposing the pixel electrode, the gate pad electrode and the data pad.
6. The array substrate according to claim 1 , wherein the pixel electrode overlaps the gate line to form a storage capacitor, wherein the gate line acts as a first electrode and the pixel electrode functions as a second electrode.
7. An array substrate for a liquid crystal display device, comprising:
a substrate;
a gate line over the substrate;
a data line crossing the gate line to define a pixel region, the data line including a transparent conductive layer and a conductive metallic layer;
a data pad at one end of the data line and including a transparent conductive layer;
a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a source electrode and a drain electrode, wherein each of the source electrode and the drain electrode includes a transparent conductive layer and a conductive metallic layer; and
a pixel electrode in the pixel region and connected to the thin film transistor,
wherein the pixel electrode and the transparent conductive layer of the drain electrode are formed of the same layer and the same material, and
wherein the transparent conductive layer of each of the source electrode and the drain electrode is disposed between the active layer and the conductive metallic layer of each of the source electrode and the drain electrode.
8. The array substrate according to claim 7 , wherein the thin film transistor includes a buffer metallic layer.
9. The array substrate according to claim 8 , wherein the buffer metallic layer is disposed between the ohmic contact layer and the transparent conductive layer of each of the source and drain electrodes.
10. The array substrate according to claim 7 , further comprising a gate pad and a gate pad electrode, wherein the gate pad is disposed at one end of the gate line and the gate pad electrode contacts the gate pad, the gate pad electrode including a transparent conductive layer.
11. The array substrate according to claim 10 , further comprising an insulating layer covering the gate line, the thin film transistor and the data line and exposing the pixel electrode, the gate pad electrode and the data pad.
12. The array substrate according to claim 7 , wherein the active layer has an island shape and is disposed over and within the gate electrode.
13. The array substrate according to claim 7 , wherein the pixel electrode overlaps the gate line to form a storage capacitor, wherein the gate line acts as a first electrode and the pixel electrode functions as a second electrode.