Security verified reconfiguration of execution datapath in extensible microcomputer
View Patent ↗Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.
1. A microprocessor architecture, comprising:
a trusted instruction set execution path;
a secure loader that evaluates security information associated with an extension as part of a loading process, the secure loader configures the reconfigurable execution path based on the security and management information, if the security information is evaluated as safe;
a reconfigurable execution path corresponding to the extension, if the security information evaluated as safe by the secure loader; and
a mechanism that determines when a fetched instruction is to be handled by the reconfigurable execution path.
2. The microprocessor architecture of claim 1 wherein the trusted instruction set execution path includes a first instruction decode block that decodes the instruction into a first set of at least one control signal fed to a multiplexer, wherein the reconfigurable execution path includes a second instruction decode block that decodes the instruction into a second set of at least one control signal fed to the multiplexer, and wherein the mechanism includes an arbiter coupled to the multiplexer to determine whether the first set or second set is output from the multiplexer.
3. The microprocessor architecture of claim 1 wherein the mechanism comprises a content addressable memory that outputs data corresponding to the fetched instruction, and wherein the data is used to determine whether the fetched instruction is to be handled by the reconfigurable execution path.
4. The microprocessor architecture of claim 1 wherein the mechanism is configurable to correspond to a computing task.
5. The microprocessor architecture of claim 1 wherein the reconfigurable execution path handles at least one instruction that the trusted instruction set execution path is not capable of handling.
6. The microprocessor architecture of claim 1 wherein the reconfigurable execution path implements a peripheral computing device.
7. The microprocessor architecture of claim 1 wherein the reconfigurable execution path handles at least one type of instruction in common with the trusted instruction set execution path to provide parallel execution paths.
8. The microprocessor architecture of claim 1 further comprising means for loading the extension, and means for evaluating metadata associated with the extension.
9. The microprocessor architecture of claim 1 wherein the reconfigurable execution path implements a peripheral device.
10. The microprocessor architecture of claim 1 further comprising, another reconfigurable execution path, wherein the mechanism determines when the fetched instruction is to be handled by the reconfigurable execution path or the other reconfigurable execution path.
11. The microprocessor architecture of claim 1 wherein the reconfigurable execution path includes an instruction fetch block, an instruction decode block, an execution block, a memory access block, and a writeback block.
12. A method comprising:
verifying security information associated with an extension;
if the security information associated with the extension is verified as safe:
loading the extension to reconfigure a microprocessor with a reconfigured execution path, such that the microprocessor includes of a plurality of execution paths including the reconfigured execution path;
fetching an instruction for execution; and
determining from the instruction which of the plurality of execution paths to use to execute the instruction.
13. The method of claim 12 wherein reconfiguring the microprocessor comprises loading an extension that changes the configuration of a set of field programmable gate arrays, and further comprising, evaluating security information associated with the extension.
14. The method of claim 12 wherein determining from the instruction which execution path to use comprises configuring an arbiter.
15. The method of claim 14 wherein configuring the arbiter comprises changing the entries in a content addressable memory.
16. The method of claim 12 wherein reconfiguring the microprocessor comprises enabling or disabling an execution path based upon at least one external criterion of a set of possible external criterion, the set including: power consumption criterion, processing power criterion, modified instruction set criterion, a computing task criterion, parallel computing criterion, peripheral configuration criterion, or application program criterion.
17. A system in a computing device, the system comprising:
a memory;
a register set comprising at least one register, and
a reconfigurable central processing unit coupled to the memory and register set, the reconfigurable central processing unit comprising:
an instruction fetch block that fetches an instruction;
means for decoding the instruction into at least one control signal;
a plurality of execution blocks that execute the instruction corresponding to the control signal or signals, including at least one execution block that is dynamically configurable;
a secure loader that evaluates security information associated with an extension block as part of a reconfiguration process, the secure loader configures the execution block that is dynamically configurable, if the security information is evaluated as safe;
means for determining which execution block handles the instruction; and
a memory access block and writeback block that writes and reads data to and from the memory block or register set as directed by the instruction.
18. The system of claim 17 wherein one of the execution blocks corresponds to a trusted execution path.
19. The system of claim 18 wherein the configurable execution block handles at least one instruction that the trusted execution path is not capable of handling.
20. The system of claim 17 wherein an execution block that is dynamically configurable is reconfigured, activated or deactivated based upon: power consumption, processing power, a need for handling a certain instruction set, a changed computing task, parallel instruction handling, a changed peripheral configuration, or an application program that is executable in the system, or based upon any combination thereof.