Semiconductor wafer pre-process annealing and gettering method and system for solar cell formation
View Patent ↗Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered. Multicrystalline semiconductor wafers having grain boundaries with impurities may also undergo the annealing and gettering of dispersed defects to the grain boundaries, further increasing the semiconductor substrate purity levels.
1. A method for pre-processing a semiconductor wafer made of low grade silicon having a thickness of approximately 150 μm or less, and having generally dispersed defects, said semiconductor wafer comprising top and bottom near-surface layers, each near-surface layer containing enhanced amounts of lattice defects predisposed to receive and hold dispersed defects and related clusters and a bulk region with dispersed defects throughout said bulk region, the method comprising:
preserving said lattice defects caused by mechanical damage occurring at said near-surface layers for permitting use of near-surface layers as a gettering site for said dispersed defects;
forming said at least one surface contaminant layer in the course of wire sawing to comprise metal atoms from the group consisting essentially of Cu, Ni, Fe in the concentration range 10 10 -10 17 metal atoms/cm 2 ; and
collecting said dispersed defects at said lattice defects in said near-surface layers by performing the steps of:
annealing said semiconductor wafer to a temperature sufficient for gettering said dispersed defects to said lattice defects and related clusters within the near-surface layers;
cooling said semiconductor wafer following said annealing step for retaining said defects as clusters predominantly within said near-surface layers, thereby increasing the impurity level of said semiconductor wafer predominantly in said near-surface layers and changing the distribution of said dispersed defects to a depth-dependent distribution within said wafers; and
removing said near-surface layers including said impurity clusters for yielding a generally higher purity level denuded zone substantially across a remaining thickness of said semiconductor wafer.
2. The method of claim 1 , further comprising the steps of forming at least one surface contaminant layer on a semiconductor wafer containing enhanced amounts of lattice defects predisposed to receive and hold defects and related clusters and removing said at least one surface contaminant layer for yielding a generally higher purity level denuded zone within said semiconductor wafer.
3. The method of claim 1 , wherein said dispersed defects comprise elements from the group consisting essentially of transition metals, metallic impurities, non-metallic impurities, lattice defects, and mixed or pure clusters of said transition metals, metallic impurities, non-metallic impurities, and lattice defects.
4. The method of claim 1 , further comprising the steps of:
forming said semiconductor wafer using a multicrystalline semiconductor, said multicrystalline semiconductor comprising generally dispersed grain boundaries within said semiconductor wafer, said generally dispersed grain boundaries comprising a threshold level of defects; and
performing said annealing step to a temperature sufficient for gettering said dispersed defects from being generally dispersed throughout said semiconductor wafer to further form impurity clusters and reaching a threshold concentration of transition metals at said generally dispersed grain boundaries, thereby increasing the purity level of said semiconductor wafer in regions from which said dispersed defects are gettered.
5. The method of claim 4 , further comprising the step of impregnating said generally dispersed grain boundaries with said threshold level of defects.
6. The method of claim 1 , further comprising the step of forming a solar cell using said semiconductor wafer.
7. The method of claim 1 , further comprising the step of forming said semiconductor wafer from a multicrystalline semiconductor ingot.
8. The method of claim 1 , further comprising the step of contaminating said at least one near-surface layer by purposely introducing high concentrations of dopant atoms into said at least one near-surface layer.
9. The method of claim 8 wherein said dopant atoms comprise phosphorous atoms in the concentration range 10 12 -10 17 atoms/cm 2 .
10. The method of claim 8 wherein said dopant atoms comprise boron atoms in the concentration range 10 12 -10 17 atoms/cm 2 .
11. The method of claim 1 , further comprising the step of annealing said semiconductor wafer using conventional furnace annealing (CFA) with ramp-up rates in the range 1-20 K/min and ramp-down rates in the range 1-20 K/min in the temperature range 400 and 1300° C.
12. The method of claim 1 , further comprising the step of annealing said semiconductor wafer using rapid thermal annealing (RTA) with ramp-up rates in the range 1-80 K/sec and ramp-down rates in the range 1-80 K/sec in the temperature range 400 and 1300° C.
13. A method, comprising:
wire sawing a low grade semiconductor wafer from a low grade semiconductor ingot;
introducing a controlled amount of a chemical solution of iron to a cut surface of the wafer in the course of wire sawing, wherein introducing a controlled amount of iron to a cut surface of the wafer includes introducing a chemical solution of iron to provide a surface concentration in a range of 10 12 -10 14 iron atoms/cm 3 ;
heating the low grade semiconductor wafer to cause migration of defects from within the low grade semiconductor wafer to at least one surface region of the low grade semiconductor wafer; and
removing the surface region.
14. The method of claim 13 , wherein wire sawing a semiconductor wafer includes wire sawing a silicon wafer.
15. The method of claim 14 , wherein wire sawing a silicon wafer includes wire sawing a multicrystalline silicon wafer.
16. The method of claim 13 , wherein wire sawing a semiconductor wafer from a semiconductor ingot includes sawing to a thickness of approximately 150 μm or less.
17. A method, comprising:
wire sawing a multicrystalline silicon wafer from a semiconductor ingot to a thickness of approximately 150 μm or less;
introducing a chemical solution of iron to a cut surface of the wafer in the course of wire sawing to provide a surface concentration in a range of 10 12 -10 14 iron atoms/cm 3 ;
heating the wafer to cause migration of defects from within the wafer to a top and bottom surface region of the wafer; and
removing approximately 10 μm of both the top and bottom surface regions to provide a substantially consistent denuded zone across a remaining thickness of the wafer.
18. The method of claim 17 , wherein heating the wafer includes using conventional furnace annealing (CFA) with ramp-up rates in the range 1-20 K/min and ramp-down rates in the range 1-20 K/min in the temperature range 400 and 1300° C.
19. The method of claim 17 , wherein heating the wafer includes using rapid thermal annealing (RTA) with ramp-up rates in the range 1-80 K/sec and ramp-down rates in the range 1-80 K/sec in the temperature range 400 and 1300° C.