IP Library › Granted Patent US 7,482,850
Granted Patent B2
US 7,482,850 · App. 11/648,652 · Granted Jan 27, 2009

Delay locked loop circuit and semiconductor integrated circuit device

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Quick Facts
Patent No.
US 7,482,850
App. No.
11/648,652
Granted
Jan 27, 2009
Kind
B2
Abstract

A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Claims (36)

1. A delay locked loop circuit comprising:

a delay locked loop element; and

a control circuit which outputs a control signal to control an operation of the delay locked loop element,

wherein the delay locked loop element is configured to receive a reference signal and the control signal, and is configured to output an output signal,

wherein the control circuit is configured to receive the reference signal and the output signal, and is configured to output the control signal,

wherein the control circuit includes an exclusive OR circuit and a counter,

wherein the exclusive OR circuit is configured to receive the reference signal and the output signal, and is configured to provide an output to the counter, and

wherein the control circuit is configured to count the output of the exclusive OR circuit using the counter, to output a first set signal by which the delay locked loop element is not operated by the control signal until the number of counts of the counter reaches a set value, and to output a second set signal by which the delay locked loop element is operated by the control signal after the number of counts of the counter reaches the set value.

2. The delay locked loop circuit according to claim 1 ,

wherein the delay locked loop element comprises a phase comparator,

wherein the phase comparator is configured to receive the reference signal, the output signal, and the control signal, and

wherein the phase comparator is configured to compare phases of the reference signal and the output signal using the control signal.

3. A delay locked loop circuit comprising:

a delay locked loop element; and

a control circuit which outputs a control signal to control an operation of the delay locked loop element,

wherein the delay locked loop element is configured to receive a reference signal and the control signal, and is configured to output an output signal,

wherein the control circuit is configured to receive the reference signal and to output the control signal,

wherein the delay locked loop element is further configured to output a feedback signal, and the control circuit is further configured to receive the feedback signal,

wherein the control circuit includes an exclusive OR circuit and a counter,

wherein the exclusive OR circuit is configured to receive the reference signal and the feedback signal, and is configured to provide an output to the counter, and

wherein the control circuit is configured to count the output of the exclusive OR circuit using the counter, to output a first set signal by which the delay locked loop element is not operated by the control signal until the number of counts of the counter reaches a set value, and to output a second set signal by which the delay locked loop element is operated by the control signal after the number of counts of the counter reaches the set value.

4. The delay locked loop circuit according to claim 3 ,

wherein the delay locked loop element comprises a phase comparator,

wherein the phase comparator is configured to receive the reference signal, the output signal, and the control signal, and

wherein the phase comparator is configured to compare phases of the reference signal and the output signal using the control signal.

5. A delay locked loop circuit comprising:

a delay locked loop element; and

a control circuit which outputs a control signal to control an operation of the delay locked loop element,

wherein the delay locked loop element is configured to receive a reference signal and the control signal, and is configured to output an output signal,

wherein the control circuit is configured to receive the reference signal and to output the control signal,

wherein the delay locked loop element is further configured to receive a standby signal,

wherein the control circuit is further configured to receive the standby signal,

wherein the control circuit includes a trimming register and a delay circuit,

wherein the trimming register is configured to output a trimming signal to the delay circuit,

wherein the delay circuit is configured to receive the standby signal and the trimming signal, and is configured to output the control signal, and

wherein the delay circuit is configured to output a signal obtained by delaying the standby signal for a specified time using the trimming signal as the control signal.