Nitrogen polar III-nitride heterojunction JFET

1. A III-nitride power semiconductor device, comprising:

an N-polar III-nitride body having an N-polar face;

a III-nitride buffer layer on said N-polar face;

a III-nitride heterojunction that includes a III-nitride barrier layer, and a III-nitride channel layer, said III-nitride heterojunction including a two-dimensional electron gas (2DEG) produced over said III-nitride barrier layer;

a first power electrode disposed over said heterojunction and coupled to said 2DEG;

a second power electrode disposed over said heterojunction and coupled to said 2DEG; and

a gate arrangement disposed over said heterojunction between said first and said second power electrode and including a P-type III-nitride body, and a gate electrode, said P-type III-nitride body being disposed between said heterojunction and said gate electrode.

2. The III-nitride device of claim 1 , wherein said barrier layer is disposed over said buffer layer and said channel layer is disposed over barrier layer.

3. The III-nitride device of claim 1 , wherein said buffer layer is comprised of GaN.

4. The III-nitride device of claim 1 , wherein aid barrier layer is comprised of AlInGaN, and aid channel layer is comprised of GaN.

5. The III-nitride device of claim 1 , wherein said P-type III-nitride body is comprised of P-type GaN.

6. The III-nitride device of claim 1 , wherein mid P-type III-nitride body is comprised of P-type AlInGaN.

7. The III-nitride device of claim 1 , further comprising a substrate, and a transition layer disposed between mid substrate and said N-polar III-nitride body.

8. The III-nitride device of claim 7 , wherein said transition layer is comprised of AlN.

9. The III-nitride device of claim 7 , wherein said transition layer is comprised of an oxide.

10. The III-nitride device of claim 7 , wherein said substrate is comprised of one of silicon, SiC, and sapphire.

11. The III-nitride device of claim 1 , further comprising a III-nitride substrate, aid N-polar III-nitride body being disposed on said III-nitride substrate.

12. The III-nitride device of claim 1 , further comprising a first spacer field plate body disposed between mid first power electrode and said gate arrangement and a second spacer field plate body disposed between said gate arrangement and said second power electrode.

13. The III-nitride device of claim 12 , wherein each spacer field plate body is at least partially under a portion of said gate arrangement.

14. The III-nitride device of claim 13 , wherein each spacer field plate body is at least partially under a portion of a respective power electrode.

15. The III-nitride device of claim 1 , wherein said power electrodes are comprised of one of Ti/Al, Ni/Au, Hf, Si.

16. The III-nitride devices of claim 1 , wherein said gate electrode is comprised of one of Ti/Al, Ni/Au, Hf, Si.

17. The III-nitride device of claim 12 , wherein said spacer field plate bodies are comprised of one of Ge, SiO 2 , Si 3 N 4 , and Al 2 O 3 .

18. A III-nitride power semiconductor device, comprising:

an N-polar III-nitride body having an N-polar face;

a III-nitride buffer layer on said N-polar face;

a III-nitride heterojunction that includes a III-nitride barrier layer, and a III-nitride channel layer, said barrier layer and said channel layer having different band gaps or different in-plane lattice constants and said III-nitride heterojunction including a two-dimensional electron gas (2DEG) formed inside said channel layer;

a first power electrode disposed over said heterojunction and coupled to said 2DEG;

a second power electrode disposed over said heterojunction and coupled to said 2DEG; and

a gate arrangement disposed over said hetero unction between said first and said second power electrode and including a P-type III-nitride body, and a gate electrode, said P-type III-nitride body being disposed between said heterojunction and said gate electrode, wherein said barrier layer is disposed over said buffer layer and said channel layer is disposed over barrier layer.