Clock generator
View Patent ↗A clock generator includes a first circuit, a second circuit, and a third circuit. The first circuit generates a first clock signal. The second circuit divides the frequency of the first clock signal to generate a second clock signal. The third circuit generates a third clock signal from the first and second clock signals. The third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level.
1. A clock generator, comprising:
a first circuit for generating a first clock signal;
a second circuit for dividing the frequency of the first clock signal to generate a second clock signal;
a third circuit for generating a third clock signal from the first and second clock signals, wherein the third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level, and
a control circuit for making the second clock signal switch between valid and invalid states in accordance with a control signal,
wherein the third circuit outputs the first clock signal as the third clock signal, when the second clock signal is in the invalid state, and
wherein the third circuit includes an OR circuit for receiving the first and second clock signals and outputting the third clock signal.
2. A clock generator, comprising:
a first circuit for generating a first clock signal;
a second circuit for dividing the frequency of the first clock signal to generate a second clock signal;
a third circuit for generating a third clock signal from the first and second clock signals, wherein the third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level, and
a control circuit for making the second clock signal switch between valid and invalid states in accordance with a control signal,
wherein the third circuit outputs the first clock signal as the third clock signal, when the second clock signal is in the invalid state, and
wherein the third circuit includes an AND circuit for receiving the first and second clock signals and outputting the third clock signal.
3. A clock generator, comprising:
a first circuit for generating a first clock signal;
a second circuit for dividing the frequency of the first clock signal to generate a second clock signal; and
a third circuit for generating a third clock signal from the first and second clock signals, wherein the third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level, wherein the second clock signal is a differential signal.
4. A clock generator, comprising:
a first circuit for generating a first clock signal;
a second circuit for dividing the frequency of the first clock signal to generate a second clock signal;
a third circuit for generating a third clock signal from the first and second clock signals, wherein the third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level; and a latch circuit for latching the second clock signal at the timing when the first clock signal changes from the first logic level to the second logic level,
wherein the third circuit receives the first clock signal and a new second clock signal generated by the latch circuit.
5. A clock generator, comprising:
a first circuit for generating a first clock signal;
a second circuit for dividing the frequency of the first clock signal to generate a second clock signal; and
a third circuit for generating a third clock signal from the first and second clock signals, wherein the third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level,
wherein the third circuit makes the third clock signal switch between valid and invalid states in accordance with a control signal.
6. A clock generator, comprising:
a first circuit for generating a first clock signal;
a second circuit for dividing the frequency of the first clock signal to generate a second clock signal;
a third circuit for generating a third clock signal from the first and second clock signals, wherein the third clock signal has the same period as that of the second clock signal, and timing at which the third clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from a first logic level to a second logic level; and a relaying circuit for outputting a new second clock signal generated from the first and second clock signals,
wherein the new second clock signal has the same period as that of the second clock signal, and timing at which the new second clock signal changes from a first logic level to a second logic level coincides with timing at which the first clock signal changes from the first logic level to the second logic level.