Piezoresistance element and semiconductor device having the same
A piezoresistance element formed in a semiconductor substrate, includes a pair of contact regions formed in the semiconductor substrate; a groove formed between the pair of contact regions; a resistance layer formed in the groove, the resistance layer having a conductive type opposing to the semiconductor substrate; and a silicon layer formed on the resistance layer, the silicon layer having a conductive type corresponding to the semiconductor substrate.
1 . A piezoresistance element formed in a semiconductor substrate, comprising:
a pair of contact regions formed in the semiconductor substrate;
a groove formed between the pair of contact regions;
a resistance layer formed in the groove, the resistance layer having a conductive type opposing to the semiconductor substrate; and
a silicon layer formed on the resistance layer, the silicon layer having a conductive type corresponding to the semiconductor substrate.
2 . A piezoresistance element according to claim 1 , wherein
the silicon layer is of a polycrystal layer.
3 . A piezoresistance element according to claim 1 , wherein
the resistance layer is a buried impurity-diffusion layer, formed by an ion implantation process of boron (B).
4 . A piezoresistance element according to claim 1 , wherein
the groove is formed by a wet-etching process.
5 . A semiconductor device having a piezoresistance element therein, wherein
the piezoresistance element comprises:
a pair of contact regions formed in the semiconductor substrate;
a groove formed between the pair of contact regions;
a resistance layer formed in the groove, the resistance layer having a conductive type opposing to the semiconductor substrate; and
a silicon layer formed on the resistance layer, the silicon layer having a conductive type corresponding to the semiconductor substrate.
6 . A semiconductor device according to claim 5 , wherein
the silicon layer is of a polycrystal layer.
7 . A semiconductor device according to claim 5 , wherein
the resistance layer is a buried impurity-diffusion layer, formed by an ion implantation process of boron (B).
8 . A semiconductor device according to claim 5 , wherein
the groove is formed by a wet-etching process.