Semiconductor device
View Patent ↗The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
1. A semiconductor device comprising:
a circuit having a first MOSFET of P type;
a well voltage controlling circuit arranged to supply a well voltage to the first MOSFET; and
a first capacitor provided between a well of the first MOSFET and the well voltage controlling circuit;
wherein the circuit has a first mode in which the circuit operates normally and a second mode in which the circuit stops operating,
wherein, during a period of power application to the semiconductor device, the well voltage controlling circuit begins to supply a first well voltage prior to an application of a first power supply voltage of the circuit,
wherein an absolute value of the first well voltage is larger than an absolute value of a second well voltage applied to the first MOSFET in the first mode; and
wherein during the first mode, the second well voltage is supplied by capacitive coupling through the first capacitor.
2. The semiconductor device according to claim 1 , wherein the circuit has a second MOSFET of N type, wherein a gate of the second MOSFET is connected to a gate of the first MOSFET and a drain of the second MOSFET is connected to a drain of the first MOSFET,
wherein the well voltage controlling circuit is arranged to supply a well voltage to the second MOSFET;
wherein, during a period of power application to the semiconductor device, the well voltage controlling circuit begins to supply a third well voltage prior to an application of the first power supply voltage of the circuit, and
wherein an absolute value of the third well voltage is larger than an absolute value of a fourth well voltage applied to the second MOSFET in the first mode.
3. The semiconductor device according to claim 2 , wherein the well voltage controlling circuit is arranged to supply the third well voltage to the second MOSFET in the second mode.
4. The semiconductor device according to claim 2 , further comprising:
a second capacitor provided between a well of the second MOSFET and the well voltage controlling circuit;
wherein during the first mode, the fourth well voltage is supplied by capacitive coupling through the second capacitor.
5. The semiconductor device according to claim 1 , wherein the well voltage controlling circuit is arranged to supply the first well voltage to the first MOSFET in the second mode.
6. The semiconductor device according to claim 1 , wherein a second power supply voltage of the well voltage controlling circuit is larger than the first power supply voltage.
7. A semiconductor device comprising:
a circuit having a first MOSFET of P type;
a well voltage controlling circuit arranged to supply a well voltage to the first MOSFET; and
a first capacitor provided between a well of the first MOSFET and the well voltage controlling circuit;
wherein the circuit has a first mode in which the circuit operates normally and a second mode in which the circuit stops operating,
wherein during the first mode, a first well voltage is supplied by capacitive coupling through the first capacitor;
wherein, during a period of power application to the semiconductor device, the well voltage controlling circuit begins to supply a second well voltage prior to an application of a power supply voltage of the circuit, and
wherein an absolute value of the second well voltage is larger than an absolute value of the first well voltage applied to the first MOSFET in the first mode.
8. A semiconductor device comprising:
a circuit having a first MOSFET of P type;
a well voltage controlling circuit arranged to supply a well voltage to the first MOSFET; and
a first capacitor provided between a well of the first MOSFET and the well voltage controlling circuit;
wherein the circuit has a first mode in which the circuit operates normally and a second mode in which the circuit stops operating,
wherein during the first mode, a first well voltage is supplied by capacitive coupling through the first capacitor;
wherein, during a period of power application to the semiconductor device, the well voltage controlling circuit begins to supply a second well voltage prior to an application of a power supply voltage of the circuit,
wherein an absolute value of the second well voltage is larger than an absolute value of the first well voltage applied to the first MOSFET in the first mode,
wherein the circuit has a second MOSFET of N type, wherein a gate of the second MOSFET is connected to a gate of the first MOSFET and a drain of the second MOSFET is connected to a drain of the first MOSFET,
wherein the well voltage controlling circuit is arranged to supply a well voltage to the second MOSFET;
wherein the semiconductor device further comprises:
a second capacitor provided between a well of the second MOSFET and the well voltage controlling circuit; and
wherein during the first mode, a third well voltage is supplied by capacitive coupling through the second capacitor.
9. The semiconductor device according to claim 8 , wherein, during a period of power application to the semiconductor device, the well voltage controlling circuit begins to supply a fourth well voltage prior to an application of a power supply voltage of the circuit, and
wherein an absolute value of the fourth well voltage is larger than an absolute value of the third well voltage applied to the second MOSFET in the first mode.