Non-volatile semiconductor memory device
View Patent ↗A cut-off circuit cuts off supply of a power supply voltage from a voltage supply circuit to a non-volatile memory block. A discharge circuit discharges an electric charge accumulated in stability capacitance. In a data retention test of the memory block, a self test circuit instructs the cut-off circuit to start operation after writing predetermined data into the memory block, and instructs the cut-off circuit to stop the operation to check retention of the predetermined data in the memory block in a predetermined time after the instruction to the cut-off circuit to start the operation. Further, in the data retention test of the memory block, the self test circuit instructs the discharge circuit to start operation along with the instruction to the cut-off circuit to start the operation, and instructs the discharge circuit to stop the operation along with the instruction to the cut-off circuit to stop the operation.
1. A semiconductor device, comprising:
plural functional blocks including a non-volatile memory block;
a voltage supply circuit supplying a power supply voltage to said functional blocks;
a cut-off circuit cutting off the supply of said power supply voltage from said voltage supply circuit to said memory block; and
a self test circuit performing tests of said functional blocks, wherein
in a data retention test of said memory block, said self test circuit instructs said cut-off circuit to start an operation after writing predetermined data into said memory block, and instructs said cut-off circuit to stop the operation to check retention of said predetermined data in said memory block in a predetermined time after the instruction to said cut-off circuit to start the operation,
wherein the voltage supply circuit supplies the power supply voltage to at least one of the plural functional blocks other than the memory block while cutting off the supply of said power supply voltage from said voltage supply circuit to said memory block.
2. The semiconductor device according to claim 1 , wherein:
said cut-off circuit comprises a voltage supply control switch connected between a power supply line and a power supply pin of said memory block, the power supply line being supplied with said power supply voltage by said voltage supply circuit; and
said voltage supply control switch is turned off in response to the instruction from said self test circuit to said cut-off circuit to start the operation, and turned on in response to the instruction from said self test circuit to said cut-off circuit to stop the operation.
3. The semiconductor device according to claim 1 , further comprising:
a stability capacitance connected between a power supply pin of said memory block and a ground line; and
a discharge circuit discharging an electric charge accumulated in said stability capacitance, wherein
in the data retention test of said memory block, said self test circuit instructs said discharge circuit to start an operation along with the instruction to said cut-off circuit to start the operation, and instructs said discharge circuit to stop the operation along with the instruction to said cut-off circuit to stop the operation.
4. The semiconductor device according to claim 3 , wherein
said discharge circuit comprises a discharge control switch connected between the power supply pin of said memory block and said ground line, and
said discharge control switch is turned on in response to the instruction from said self test circuit to said discharge circuit to start the operation and turned off in response to the instruction from said self test circuit to said discharge circuit to stop the operation.
5. The semiconductor device according to claim 3 , wherein
said stability capacitance is constituted of a ferroelectric capacitance.
6. The semiconductor device according to claim 1 , wherein
said memory block is constituted of a ferroelectric memory.
7. A semiconductor device, comprising:
plural functional blocks including a non-volatile memory block;
a voltage supply circuit supplying a first power supply voltage to said memory block and supplying a second power supply voltage to at least one of said functional blocks except said memory block;
a cut-off circuit cutting off the supply of said first power supply voltage from said voltage supply circuit to said memory block; and
a self test circuit performing tests of said functional blocks, wherein
in a data retention test of said memory block, said self test circuit instructs said cut-off circuit to start an operation after writing predetermined data into said memory block, and instructs said cut-off circuit to stop the operation to check retention of said predetermined data in said memory block in a predetermined time after the instruction to said cut-off circuit to start the operation,
wherein the voltage supply circuit supplies the second power supply voltage to at least one of the plural functional blocks other than the memory block while cutting off the supply of said first power supply voltage from said voltage supply circuit to said memory block.
8. The semiconductor device according to claim 7 , further comprising:
a stability capacitance connected between a power supply pin of said memory block and a ground line; and
a discharge circuit discharging an electric charge accumulated in said stability capacitance, wherein
in the data retention test of said memory block, said self test circuit instructs said discharge circuit to start an operation along with the instruction to said cut-off circuit to start the operation, and instructs said discharge circuit to stop the operation along with the instruction to said cut-off circuit to stop the operation.
9. The semiconductor device according to claim 7 , wherein
said voltage supply circuit comprises:
a first voltage generating circuit generating said first power supply voltage using an external input voltage; and
a second voltage generating circuit generating said second power supply voltage by stepping down said first power supply voltage.
10. The semiconductor device according to claim 7 , wherein
said voltage supply circuit comprises:
a first voltage generating circuit generating said second power supply voltage using an external input voltage; and
a second voltage generating circuit generating said first power supply voltage by boosting said second power supply voltage.