Display control semiconductor integrated circuit
View Patent ↗The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without significantly increasing the occupation area. A liquid crystal controller/driver in which a RAM for storing display data is provided in a chip and the storage capacity of the built-in RAM is determined according to the size of a display screen of a liquid crystal panel to be driven, includes a fuse circuit for setting a defect address, and a comparing circuit for comparing the defect address set in the fuse circuit with an input address. The liquid crystal controller/driver also has a redundant circuit, when the addresses match each other, for replacing the input address with an address that instructs the spare memory area and supplying the address to an address decoder.
1. A display control semiconductor integrated circuit comprising:
a readable/writable display memory having a storage area smaller than an address space of the n-th power of 2, which can be expressed by an address made by a binary code of n bits (where n is an integer), and storing display data in the storage area, wherein the display memory has a spare storage area in addition to a normal storage area for storing display data;
a repair circuit for performing defect repair by replacing an area including a defect in the display memory with the spare storage area is provided;
an address setting register for setting an area for displaying a window in a display screen;
repair information setting means for setting address information of an area including a defect in the display memory;
an address comparing circuit for comparing an address set in the repair information setting means with an input address supplied to the display memory;
an address replacing circuit;
a first address counter for generating an address for writing data to the display memory;
a second address counter for generating an address for reading data from the display memory;
a first address comparing circuit for comparing an address generated by the first address counter with an address set in the repair information setting means; and
a second address comparing circuit for comparing an address generated by the second address counter with the address set in the repair information setting means,
wherein the address replacing circuit is configured to replace an address when a match of addresses is detected by the first or second address comparing circuit,
wherein, when the address comparing circuit detects a match of the addresses, the address replacing circuit is configured to replace the input address supplied to the display memory with an address designating the spare storage area,
wherein, when address information of the area including a defect in the display memory is not set, the repair information setting means indicated an address out of the address range of the normal storage area and the spare storage area in the address space,
wherein the address of the spare storage area is set on the outside of an address range in which and address can be set by the register,
wherein an address of the spare storage area is set in the address space and on the outside of a range of addresses of the normal storage area, and
wherein the repair information setting means does not include means for setting information indication whether an area including a defect in the display memory id replaced with the spare memory area or not.
2. The display control semiconductor integrated circuit according to claim 1 ,
wherein the display memory has an address decoder, and the address decoder selects the normal storage area and the spare storage area on the basis of a common input address.
3. The display control semiconductor integrated circuit according to claim 1 ,
wherein the address replacing circuit is a combinational logic circuit comprising a plurality of logic gate circuits configured to receive an address input to the address comparing circuit and an output of the address comparing circuit, and to output an address that designates the spare storage area by a logic operation.
4. The display control semiconductor integrated circuit according to claim 1 ,
wherein replacement of an area including a defect in the display memory with the spare storage area by the repairing circuit is performed in the unit of a word as the storage area in the display memory corresponding to one display line in a display device.
5. The display control semiconductor integrated circuit according to claim 1 , further comprising:
a write inhibit control circuit including a third address comparing circuit for detecting whether an address generated by the first address counter lies in an address range of the normal storage area or not and, when the third address comparing circuit determines that an address generated by the first address counter does not lie in the address range of the normal storage area, the write inhibit control circuit is configured to generate and output a signal inhibiting writing of data to the display memory.
6. The display control semiconductor integrated circuit according to claim 5 ,
wherein the display memory has an address decoder, and the address decoder selects the normal storage area and the spare storage area on the basis of a common input address.
7. The display control semiconductor integrated circuit according to claim 5 ,
wherein the address replacing circuit is a combinational logic circuit comprising a plurality of logic gate circuits configured to receive an address input to the address comparing circuit and an output of the address comparing circuit, and to output an address that designates the spare storage area by a logic operation.
8. The display control semiconductor integrated circuit according to claim 5 ,
wherein replacement of an area including a defect in the display memory with the spare storage area by the repairing circuit is performed in the unit of a word as the storage area in the display memory corresponding to one display line in a display device.