Signal transmission method, bridge unit, and information processing apparatus
View Patent ↗An information processing apparatus having a fat tree structure, in which signal transmission across node columns managed by respective processor units is performed through end point bridges included in bridge chips. In this transmission method, the bridge chips perform routing by using node IDs that are given to the respective node columns and levels that indicate the hierarchical depths of the bridge chips, thereby selecting the shortest routes of signals.
1. A signal transmission method for transmitting a signal to be transmitted between different processor units in an information processing apparatus having a fat tree structure including a plurality of processor units, the method comprising:
issuing a signal from one of the processor units; and
relaying the signal by a plurality of bridge units, wherein
the relaying of the signal includes:
inputting the signal to a bridge unit; and
selecting which bus to output to and outputting the signal thereto based on a number of a column to which the bridge unit belongs, the number being given to each column consisting of a processor unit and bridge units managed by the processor unit in a matrix of the fat tree structure, a level number of a row to which the bridge unit belongs, the level number being given to each row consisting of bridge units in the matrix, and a number of a column of bridge units managed by a destination processor unit.
2. The signal transmission method according to claim 1 , wherein the relaying of the signal includes selecting which bus to output to so that the signal to be transmitted via the plurality of bridge units reaches the destination processor unit with only a single turn in direction from downstream to upstream.
3. The signal transmission method according to claim 1 , wherein the relaying of the signal includes outputting the signal through a bridge for relaying an end point of a bus managed by the processor unit managing the bridge unit and an end point of a bus managed by another processor unit, to a bridge unit managed by the another processor unit in accordance with the selection.
4. The signal transmission method according to claim 3 , wherein the relaying of the signal includes selecting which bus to output to so that the signal to be transmitted via a plurality of bridge units reaches the destination processor unit with only a single turn in direction from downstream to upstream.
5. The signal transmission method according to claim 1 , wherein the relaying of the signal includes referring to binary bit strings indicating the number of a column to which the bridge unit belongs and the number of the column of bridge units managed by the destination processor unit when selecting which bus to output.
6. A bridge unit for relaying a signal to be transmitted between different processor units in an information processing apparatus having a fat tree structure including a plurality of processor units, the bridge unit comprising:
a plurality of bus bridges;
an end point bridge which relays signal transmission between end points of two device trees managed by two respective processor units; and
a switch routing circuit which selects which bus to output an input signal to, wherein
the switch routing circuit includes a register which sets a number of a column to which the bridge unit belongs, the number being given to each column consisting of a processor unit and bridge units managed by the processor unit in a matrix of the fat tree structure, and a level number of a row to which the bridge unit belongs, the level number being given to each row consisting of bridge units in the matrix, and
the switch routing circuit selects which bus to output to based on the number of the column and the level number set in the register and a number of column of bridge units managed by a destination processor unit for the input signal to be transmitted to, and controls output accordingly so that the signal passes through any one of the bus bridges and the end point bridge.
7. The bridge unit according to claim 6 , wherein:
the switch routing circuit has a mode for practicing a routing rule based on a parameter different from the number of the column and the level number; and
the bridge unit farther comprises a multiplexer which selects any one of output signals from the end point bridge and the bus bridges as a valid output signal depending on if the mode is selected by a user.
8. The bridge unit according to claim 6 , wherein
the fat tree structure includes 2 n processor units, and
when the bridge unit has a level number m of 0<m<n:
the switch routing circuit outputs a signal input from an upstream side of the bridge unit to an arbitrary bus downstream
if
tn[n− 1 :m]≠bn[n− 1 :m ], and
outputs the signal to a bridge unit belonging to a column having a binary sequence of bn′[n−1:0] in which
bn′[m− 1 ]=tn[m− 1]
if
tn[n− 1 :m]=bn[n− 1 :m ]; and
the switch routing circuit always outputs a signal input from a downstream side of the bridge unit to a bridge unit belonging to a column having a binary sequence of bn′[n−1:0] in which
bn′[m− 1 ]=tn[m− 1],
where tn[n−1:0] is the binary sequence of the number of a column of bridge units managed by the destination processor unit, and bn[n−1:0] is the binary sequence of the number of a column to which the bridge unit belongs.
9. The bridge unit according to claim 8 , wherein:
the switch routing circuit has a mode for practicing a routing rule based on a parameter different from the number of the column and the level number; and
the bridge unit further comprises a multiplexer for selecting any one of output signals from the end point bridge and the bus bridges as a valid output signal depending on if the mode is selected by a user.
10. An information processing apparatus comprising:
a plurality of processor units; and
a bridge unit which relays a signal to be transmitted between different processor units,
the bridge unit including:
a bus bridge which relays signal transmission within a device tree managed by a single processor unit;
an end point bridge which relays signal transmission between end points of two device trees managed by two respective processor units; and
a switch routing circuit which selects either one of the bus bridge and the end point bridge to which an input signal to be transmitted between different processor units is output so that the input signal reaches a destination processor unit through a shortest route, based on a column number and a row number in a matrix consisting of the bridge units.
11. A bridge unit for relaying a signal to be transmitted between different processor units in an information processing apparatus having a fat tree structure including a plurality of processor units, the bridge unit comprising:
a plurality of bus bridges;
an end point bridge which relays signal transmission between end points of two device trees managed by two respective processor units; and
a switch routing circuit which selects which bus to output an input signal to, wherein
the switch routing circuit includes a register which sets an identification number of a column in the fat tree structure to which the bridge unit belongs, and a level number of a row to which the bridge unit belongs, and
the switch routing circuit selects which bus to output to based on the identification number and the level number set in the register and an identification number of column of bridge units managed by a destination processor unit for the input signal to be transmitted to, and controls output accordingly so that the signal passes through any one of the bus bridges and the end point bridge, wherein
the fat tree structure includes 2 n processor units, and the bridge unit has a level number m of 0<m<n:
the switch routing circuit outputs a signal input from an upstream side of the bridge unit to an arbitrary bus downstream
if
tn [n− 1 :m]≠bn [n− 1 :m ], and
outputs the signal to a bridge unit belonging to a column having a binary sequence of identification number bn′ [n−1:0] in which bn′ [m−1]=tn [m−1]
if
tn [n− 1 :m]≠bn [n− 1 :m ]; and
the switch routing circuit always outputs a signal input from a downstream side of the bridge unit to a bridge unit belonging to a column having a binary sequence to identification number bn′ [n−1:0] in which
bn′ [m− 1 ]=tn[m− 1],
where tn [n−1:0] is the binary sequence of identification number of a column of bridge units managed by a destination processor unit for the input signal to be transmitted to, and bn [n−1:0] is the binary sequence of identification number of the bridge unit.