Semiconductor device including bus with signal lines
A semiconductor memory device has the group of longest signal lines configured in a twisted wiring scheme, the group of signal lines of intermediate length configured in a shield wiring scheme, and the group of shortest signal lines configured in a single wiring scheme. As a whole, degradation in signal waveform and improvement in layout efficiency can both be achieved.
1 . A semiconductor device including a bus formed of a plurality of signal lines, said plurality of signals lines configured in a plurality of wiring schemes.
2 . The semiconductor device according to claim 1 , wherein
said plurality of signal lines differ in length, and
the wiring scheme of each signal line is determined according to the length of the signal line.
3 . The semiconductor device according to claim 1 , wherein said plurality of wiring schemes include at least two wiring schemes among three wiring schemes corresponding to a twisted wiring scheme of twisting each signal line with another signal line, a shield wiring scheme of arranging a shield line between two adjacent signal lines, and a single wiring scheme of not twisting signal lines together and not arranging a shield line.
4 . The semiconductor device according to claim 3 , wherein
said plurality of signal lines include a first signal line, and a signal second signal line longer than said first signal line,
said first signal line is configured in said single wiring scheme, and
said second signal line is configured in said shield wiring scheme or said twisted wiring scheme.
5 . The semiconductor device according to claim 3 , wherein
said plurality of signal lines include a first signal line and a second signal line longer than said first signal line,
said first signal line is configured in said shield wiring scheme, and
said second signal line is configured in said twisted wiring scheme.
6 . The semiconductor device according to claim 3 , wherein
said plurality of signal lines includes a first signal line, a second signal line longer than said first signal line, and a third signal line longer than said second signal line,
said first signal line is configured in said single wiring scheme,
said second signal line is configured in said shield wiring scheme,
said third signal line is configured in said twisted wiring scheme.