Memory, processing system and methods for use therewith
View Patent ↗A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column enable signal. A sense amplifier produces a data output.
1. A processing system comprising:
a processor,
memory device, operably coupled to the processor, the memory device including:
an array of memory cells;
a selected bitline operably, coupled to the array of memory cells, that is precharged to produce a precharged bitline signal;
a column voltage booster, operably coupled to a column enable signal, to produce a boosted column enable signal;
a column multiplexer, having a first node coupled to the selected bitline and a second node coupled to a sense amplifier input, for passing the precharged bitline signal to the sense amplifier input in response to the boosted column enable signal; and
a sense amplifier, operably coupled to the sense amplifier input, for producing a data output.
2. The processing system of claim 1 further comprising:
an n-channel, metal oxide semiconductor (NMOS) transistor, operably coupled to the selected bitline, for passing the precharged bitline signal on the selected bitline even when the signal has drifted above a precharge threshold.
3. The processing system of claim 1 wherein the column multiplexer includes an n-channel metal oxide semiconductor (NMOS) transistor.
4. A memory comprising:
an array of memory cells;
a selected bitline, operably coupled to the array of memory cells, that is precharged to produce a precharged bitline signal;
a column voltage booster, operably coupled to a column enable signal, to produce a boosted column enable signal;
a column multiplexer, having a first node coupled to the selected bitline and a second node coupled to a sense amplifier input, for passing the precharged bitline signal to the sense amplifier input in response to the boosted column enable signal; and
a sense amplifier, operably coupled to the sense amplifier input, for producing a data output.
5. The memory of claim 4 further comprising:
an n-channel metal oxide semiconductor (NMOS) transistor, operably coupled to the selected bitline, for passing the precharged bitline signal on the selected bitline even when the signal has drifted above a precharge threshold.
6. The memory of claim 4 wherein the column multiplexer includes an n-channel metal oxide semiconductor (NMOS) transistor.