Semiconductor device and method for manufacturing the same for improving the performance of mis transistors
View Patent ↗An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.
1. A semiconductor device comprising:
a single MIS transistor including an active region formed in a semiconductor substrate, a gate electrode formed on the active region, and source and drain regions formed in the active region;
a stress control film being in direct contact with the semiconductor substrate, the source region, the drain region, and the gate electrode, and covering the semiconductor substrate, the source region, the drain region, and the gate electrode; and
an interlayer insulating film stacked on the stress control film to be in direct contact with the stress control film, wherein:
a direction of length of a channel connecting the source region and the drain region is parallel to the <100> crystallographic axis of the semiconductor substrate,
the stress control film has a pair of openings formed to sandwich the gate electrode of only the single MIS transistor such that both ends of the gate electrode in a gate width direction are located between the pair of openings when viewed in plan, and
the interlayer insulating film and the semiconductor substrate are in direct contact with each other in the pair of openings.
2. The semiconductor device of claim 1 , further comprising:
an isolation region formed in a region surrounding the active region in the semiconductor substrate, and
the pair of openings are formed on the isolation region.
3. The semiconductor device of claim 1 , wherein
the active region is formed in the semiconductor substrate around a surface of the semiconductor substrate.
4. The semiconductor device of claim 1 , wherein
the pair of openings are longer than the gate electrode in a gate length direction of the gate electrode.
5. The semiconductor device of claim 1 , wherein the single MIS transistor is an n-channel type MIS transistor.
6. The semiconductor device of claim 1 , wherein the stress control film is an insulating film.