Nonvolatile semiconductor memory device and its fabrication method
View Patent ↗A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.
1. A semiconductor device comprising a split-gate memory cell, the memory cell including:
a selective gate formed on a principal surface of a semiconductor substrate through a gate insulating layer;
a memory gate formed on one side surface of the selective gate, the memory gate being in a form of a sidewall; and
an ONO layer with a generally L-shaped cross section, includes one part formed between one side surface of the selective gate and one side surface of the memory gate, and an other part formed below the memory gate,
wherein a second insulating layer is formed on an other side surface of the memory gate through a first insulating layer, the first insulating layer being in the form of a sidewall, the second insulating layer also being in the form of a sidewall,
the second insulating layer in the form of the sidewall is formed on an other side surface of the selective gate, and
one end of the ONO layer formed on the semiconductor substrate is terminated below the first insulating layer.
2. The semiconductor memory device according to claim 1 ,
wherein hot electrons generated in the semiconductor substrate are injected into the ONO layer by applying a first voltage to the semiconductor substrate near the memory gate and a second voltage higher than the first voltage to the memory gate during a write operation.
3. The semiconductor memory device according to claim 2 ,
wherein an erasing operation is performed by injecting holes into the ONO layer into which the hot electrons have been injected.