Method and apparatus for counting instructions during speculative execution

1. A method for counting speculatively-executed instructions for performance analysis purposes, comprising:

counting instructions which are normally executed during a normal-execution mode on a processor, wherein counting instructions involves incrementing an instruction counter when an instruction is executed during the normal-execution mode;

entering a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor, wherein the speculative-execution mode includes:

an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; and

a deferred mode wherein deferred instructions are executed in program order, and wherein deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again;

checkpointing a value of the instruction counter;

counting the speculatively-executed instructions during the speculative-execution mode, wherein counting the speculatively-executed instructions involves incrementing the instruction counter as an instruction is encountered during the execute-ahead mode even if the instruction is deferred, and not counting any deferred instructions when the deferred instructions are executed in deferred mode; and

if the speculative-execution mode does not complete successfully, restoring the value of the instruction counter from the checkpoint.

2. The method of claim 1 ,

wherein if the speculative-execution mode completes successfully, the method further comprises committing results of the speculative execution to the architectural state of the processor.

3. The method of claim 1 ,

wherein at least one of counting the instructions which are normally executed during the normal-execution mode and counting the speculatively-executed instructions also involves counting cycles required to execute the instructions; and

wherein the method further comprises computing a cycles per instruction (CPI) value based on the counted cycles and at least one of the counted instructions which are normally executed during the normal-execution mode and the counted speculatively-executed instructions.

4. The method of claim 1 , wherein at least one of counting the instructions which are normally executed during the normal-execution mode and counting the speculatively-executed instructions involves using one or more hardware counters to count the instructions.

5. The method of claim 1 , wherein checkpointing the value of the instruction counter involves generating a checkpoint that includes the value of the instruction counter before entering the speculative-execution mode.

6. The method of claim 1 , wherein at least one of counting the instructions which are normally executed during the normal-execution mode and counting the speculatively-executed instructions involves counting one or more of the following:

all instructions executed;

non-privileged instructions executed;

privileged instructions executed;

memory operations performed;

floating-point instructions executed;

cache misses generated;

instructions of a given type; and

events that occur during instruction execution.

7. An apparatus that counts speculatively-executed instructions for performance analysis purposes, comprising:

a processor;

wherein the processor is configured to count instructions which are normally executed during a normal-execution mode on a processor, wherein counting instructions involves incrementing an instruction counter when an instruction is executed during the normal-execution mode;

wherein the processor is configured to enter a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor, wherein the speculative-execution mode includes:

an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; and

a deferred mode wherein deferred instructions are executed in program order, and wherein deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again;

wherein the processor is configured to checkpoint a value of the instruction counter;

wherein the processor is configured to count the speculatively-executed instructions during the speculative-execution mode, wherein counting the speculatively-executed instructions involves incrementing the instruction counter as an instruction is encountered during the execute-ahead mode even if the instruction is deferred, and not counting any deferred instructions when the deferred instructions are executed in deferred mode; and

wherein if the speculative-execution mode does not complete successfully, the processor is configured to restore the value of the instruction counter from the checkpoint.

8. The apparatus of claim 7 ,

wherein if the speculative execution completes successfully, the processor is configured to commit results of the speculative execution to the architectural state of the processor.

9. The apparatus of claim 7 ,

wherein at least one of counting the instructions which are normally executed during the normal-execution mode and counting the speculatively-executed instructions also involves counting cycles required to execute the instructions; and

wherein the processor is configured to compute a cycles per instruction (CPI) value based on the counted instructions and the counted cycles.

10. The apparatus of claim 7 , wherein the processor includes one or more hardware counters to count at least one of the instructions which are normally executed during the normal-execution mode and the speculatively-executed instructions.

11. The apparatus of claim 7 , wherein the processor is configured to generate a checkpoint that includes the value of the instruction counter before entering the speculative-execution mode.

12. The apparatus of claim 7 , wherein at least one of the instructions which are normally executed during the normal-execution mode which are counted and the speculatively-executed instructions which are counted can include one or more of the following:

all instructions executed;

non-privileged instructions executed;

privileged instructions executed;

memory operations performed;

floating-point instructions executed;

cache misses generated;

instructions of a given type; and

events that occur during instruction execution.

13. A computer system that counts speculatively-executed instructions for performance analysis purposes, comprising:

a processor; and

a memory;

wherein the processor is configured to count instructions which are normally executed during a normal-execution mode on the processor, wherein counting instructions involves incrementing an instruction counter when an instruction is executed during the normal-execution mode;

wherein the processor is configured to enter a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor, wherein the speculative-execution mode includes:

an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order; and

a deferred mode wherein deferred instructions are executed in program order, and wherein deferred instructions that still cannot be executed because of unresolved data dependencies are deferred again;

wherein the processor is configured to checkpoint a value of the instruction counter;

wherein the processor is configured to count the speculatively-executed instructions during the speculative-execution mode, wherein counting the speculatively-executed instructions involves incrementing the instruction counter as an instruction is encountered during the execute-ahead mode even if the instruction is deferred, and not counting any deferred instructions when the deferred instructions are executed in deferred mode; and

wherein if the speculative-execution mode does not complete successfully, the processor is configured to restore the value of the instruction counter from the checkpoint.

14. The computer system of claim 13 ,

wherein if the speculative execution completes successfully, the processor is configured to commit results of the speculative execution to the architectural state of the processor.

15. The computer system of claim 13 , wherein at least one of the instructions which are normally executed during the normal-execution mode which are counted and the speculatively-executed instructions which are counted can include one or more of the following:

all instructions executed;

non-privileged instructions executed;

privileged instructions executed;

memory operations performed;

floating-point instructions executed;

cache misses generated;

instructions of a given type; and

events that occur during instruction execution.