Non-volatile memory
View Patent ↗A non-volatile memory cell includes an upper electrode; a lower electrode and a state-variable region, in which a conductive state changes only once. The state variable region is formed in a region between the upper electrode and the lower electrode. The state-variable region comprises a first semiconductor layer of a first conductive type; and second semiconductor layers of a second conductive type, opposing to the first conductive type, which are formed on upper and lower surfaces of the first semiconductor layer via PN junctions.
1. A non-volatile memory cell to store data, comprising:
an upper electrode and a lower electrode; and
a state-variable region, in which a conductive state changes permanently, the state variable region being disposed between and in electrical contact with each of the upper electrode and the lower electrode,
wherein the state-variable region comprises a first semiconductor layer of a first conductive type and second semiconductor layers of a second conductive type on either side of the first semiconductor layer in a direction of current flow through the state-variable region, which form on upper and lower surfaces of the first semiconductor layer two PN junctions of opposite polarity orientations;
whereby the memory cell has four possible states depending on which of the two PN junctions has been broken and not broken, and two bits of data are storable in the memory cell.
2. The non-volatile memory according to claim 1 , wherein
at least one of the upper and lower electrodes comprises the second semiconductor layer.
3. The non-volatile memory according to claim 1 , wherein
the second semiconductor layer is of a poly-silicon of p-type or n-type.
4. The non-volatile memory according to claim 1 , comprising insulation disposed between the upper electrode and the lower electrode, and wherein the state-variable region is disposed within a via hole in the insulation.
5. The non-volatile memory according to claim 1 , wherein the state variable region is in direct contact with each of the upper electrode and the lower electrode.
6. The non-volatile memory according to claim 1 , wherein the state variable region consists of the first conductive layer and the two second semiconductor layers of a second conductive type on either side of the first semiconductor layer in the direction of current flow through the state-variable region, which form on the upper and lower surfaces of the first semiconductor layer the two PN junctions of opposite polarity orientations.
7. The non-volatile memory according to claim 6 , comprising insulation disposed between the upper electrode and the lower electrode, and wherein the state-variable region is disposed within a via hole in the insulation.
8. The non-volatile memory according to claim 6 , wherein the state variable region is in direct contact with each of the upper electrode and the lower electrode.
9. The non-volatile memory according to claim 6 , wherein at least one of the upper and lower electrodes comprises the second semiconductor layer.