IP Library Granted Patent US 7,948,291
Granted Patent B2
US 7,948,291 · App. 11/661,132 · Granted May 24, 2011

Logic circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,948,291
App. No.
11/661,132
Granted
May 24, 2011
Kind
B2
Abstract

The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth 1 ) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth 2 ) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.

Claims (18)

1. A logic circuit, comprising:

a switching device having two different stable resistivity values for each applied voltage value that is greater than a prescribed first threshold voltage, and is smaller than a prescribed second threshold voltage that is larger than the prescribed first threshold voltage, which when a voltage less than or equal to the prescribed first threshold voltage is applied thereto, becomes in a first state having the higher resistivity value of the two different stable resistivity values, and when a voltage more than or equal to the prescribed second threshold voltage is applied thereto, becomes in a second state having the lower resistivity value of the two different stable resistivity values, the switching device having first and second ends, including:

a lower electrode layer and an upper electrode layer, each of which is made of a thin film, and

an organic bistable layer, which is made of a thin film mediated between the lower electrode layer and the upper electrode layer, wherein

the lower electrode layer and the upper electrode layer are formed such that they are each in a stripe form and that their longitudinal axial lines are orthogonal to each other; and

the organic bistable layer is formed so as to cover an intersection point between the lower electrode layer and the upper electrode layer;

a resistance device connected to the second end of the switching device to form a series circuit;

a bias terminal for applying a prescribed bias voltage to both ends of the series circuit of the switching device and the resistance device;

a first pulse inputting terminal for inputting a first pulse of a first prescribed voltage to the first end of the switching device;

a second pulse inputting terminal for inputting a second pulse of a second prescribed voltage to a connection between the second end of the switching device and the resistance device, the first and second states being selectively generated in the switching device by a combination of inputs of the first and second pulses; and

an output terminal for outputting an output voltage according to the first and second states, wherein

the bias terminal and the first pulse inputting terminal are connected to the upper electrode layer, and

the output terminal and the second pulse inputting terminal are connected to the lower electrode layer.

2. The logic circuit according to claim 1 , wherein

the lower electrode layer and the upper electrode layer comprise aluminum; and

the organic bistable layer comprises aminoimidazole dicyanate.

3. The logic circuit according to claim 1 , wherein the longitudinal axial line of the upper electrode layer is parallel to the longitudinal axial line of the first pulse inputting terminal, and orthogonal to the longitudinal axial line of the bias terminal.

4. The logic circuit according to claim 1 , wherein the longitudinal axial line of the lower electrode layer is parallel to the longitudinal axial line of the second pulse inputting terminal, and orthogonal to the longitudinal axial line of the output terminal.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Aug 26, 2011
From: FUJI ELECTRIC HOLDINGS CO., LTD.
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 026891/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2008
From: KAWAKAMI, HARUO
To: FUJI ELECTRIC HOLDINGS CO., LTD.
Reel/Frame 021125/0115 →