Instruction-based timer control during debug
View Patent ↗A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.
1. A processing device comprising:
a first timer;
a processor core configured to execute a first instruction during a debug session of a debug mode of the processor core; and
a timer control module configured to selectively enable/disable the first timer based on a comparison of a first characteristic of the first instruction to a criterion, the first characteristic comprising at least one of an instruction type of the first instruction or an instruction source of the first instruction.
2. The processing device of claim 1 , wherein the first timer is selected from a group consisting of: a watchdog timer; a decrement timer; and a time-base timer.
3. The processing device of claim 1 , wherein the first characteristic comprises the instruction type of the first instruction and the criterion comprises a predetermined instruction type.
4. The processing device of claim 1 , wherein the first characteristic comprises the instruction source of the first instruction and the criterion comprises a predetermined instruction source.
5. The processing device of claim 1 , further comprising:
a second timer; and
wherein the timer control module is configured to selectively enable/disable the second timer based on the first characteristic of the first instruction.
6. The processing device of claim 1 , further comprising:
a second timer; and
wherein the timer control module is configured to selectively enable/disable the second timer based on a second characteristic of the first instruction, the second characteristic different than the first characteristic.
7. The processing device of claim 1 , wherein:
the processor core is configured to execute a second instruction during the debug session; and
the timer control module is configured to selectively enable/disable the first timer based on a second characteristic of the second instruction.
8. The processing device of claim 1 , further comprising:
an external debug interface;
a debug control register accessible via the external debug interface; and
wherein the timer control module further is configured to selectively enable/disable the first timer based on at least one bit value of the debug control register.
9. The processing device of claim 1 , wherein the timer control module is configured to enable the first timer in response to the first characteristic meeting the criterion and configured to disable the first timer in response to the first characteristic not meeting the criterion.
10. The processing device of claim 1 , wherein the timer control circuitry is configured to disable the first timer in response to the first characteristic meeting the criterion and configured to enable the first timer in response to the first characteristic not meeting the criterion.
11. A method comprising:
receiving an instruction for execution at a processing device during a debug session of a debug mode of the processing device;
determining a characteristic of the instruction, the characteristic comprising at least one of an instruction type of the instruction or an instruction source of the instruction; and
selectively enabling/disabling a timer of the processing device based on a comparison of the characteristic to a criterion.
12. The method of claim 11 , wherein selectively enabling/disabling the timer based on the characteristic comprises enabling the timer during an execution of the instruction based on the comparison of the characteristic to the criterion.
13. The method of claim 11 , wherein the timer is a first timer, and the method further comprises selectively enabling/disabling a second timer of the processing device based on the characteristic.
14. The method of claim 1 , wherein the timer is a first timer and the characteristic is a first characteristic, and the method further comprises selectively enabling/disabling a second timer of the processing device based on a second characteristic of the instruction that is different than the first characteristic.
15. The method of claim 11 , wherein selectively enabling/disabling the timer comprises selectively enabling/disabling the timer further based on at least one bit value of a debug control register of the processing device accessible via an external debug interface.
16. The method of claim 11 , wherein:
the characteristic is an instruction type of the instruction and the criterion is a predetermined instruction type.
17. The method of claim 11 , wherein:
the characteristic is an instruction source of the instruction and the criterion is a predetermined instruction source.
18. The method of claim 11 , wherein the timer is selected from a group consisting of: a watchdog timer; a decrement timer; and a time-base timer.
19. A processing device comprising:
a timer;
a processor core configured to execute an instruction during a debug session of a debug mode of the processor core;
an external debug interface;
a debug control register accessible via the external debug interface; and
a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction and at least one bit value of the debug control register.
20. The processing device of claim 19 , wherein the timer is selected from a group consisting of: a watchdog timer; a decrement timer; and a time-base timer.