Numerical full well capacity extension for photo sensors with an integration capacitor in the readout circuit using two and four phase charge subtraction

1. A detector circuit comprising:

an amplifier;

a switch matrix;

an integration capacitor coupled to the amplifier via the switch matrix, the integration capacitor is operable in two or more phases, the switch matrix is configured to phase switch the integration capacitor, wherein the phase switch inverts a polarity of the integration capacitor; and

a comparator coupled to the amplifier, the comparator triggers the phase switch when an output voltage of the amplifier passes a threshold voltage of the comparator.

2. The detector circuit of claim 1 wherein the amplifier is a charge trans-impedance amplifier.

3. The detector circuit of claim 1 wherein the switch matrix has two switches on each side of the integration capacitor.

4. The detector circuit of claim 1 wherein the comparator is a Schmitt trigger.

5. The detector circuit of claim 1 further comprising a counter coupled to the comparator, the counter receives a signal from the comparator when the output voltage of the amplifier is greater than the threshold voltage of the comparator, the counter triggers the switch matrix to phase switch.

6. A detector circuit comprising:

a transistor;

a switch matrix;

an integration capacitor coupled to the transistor via the switch matrix, the integration capacitor is operable in two phases, the switch matrix is configured to phase switch the integration capacitor, wherein the phase switch inverts a polarity of the integration capacitor; and

a comparator coupled to the transistor, the comparator triggers the phase switch when an output voltage of the transistor passes a threshold voltage of the comparator.

7. The detector circuit of claim 6 wherein the transistor is a direct injection field effect transistor.

8. The detector circuit of claim 6 wherein the switch matrix has two switches on each side of the integration capacitor.

9. The detector circuit of claim 6 wherein the comparator is a Schmitt trigger.

10. The detector circuit of claim 6 further comprising a counter coupled to the comparator, the counter receives a signal from the comparator when the output voltage of the transistor passes the threshold voltage of the comparator, the counter triggers the switch matrix to phase switch.

11. A detector circuit comprising:

an integration capacitor having a first and a second plate, the integration capacitor is operable in two or more phases;

a first and a second switch connected to the first plate of the integration capacitor, the first and second switches are configured to phase switch the integration capacitor through the opening and closing of the first and second switches;

a third and a fourth switch connected to the second plate of the integration capacitor, the third and fourth switches are configured to phase switch the integration capacitor through the opening and closing of the third and fourth switches;

an amplifier coupled to the integration capacitor; and

a comparator coupled to the amplifier and a counter, the comparator outputs a signal to the counter when an output voltage of the amplifier passes a threshold voltage of the comparator, the counter receives the signal from the comparator and triggers the first, second, third or fourth switches to phase switch.

12. The detector circuit of claim 11 wherein the amplifier is a charge trans-impedance amplifier.

13. The detector circuit of claim 11 wherein the comparator is a Schmitt trigger.

14. The detector circuit of claim 11 wherein the phase switch inverts the polarity of the integration capacitor.

15. A method for reducing noise in a detector circuit, the detector circuit includes a photodiode, an amplifier, a first capacitor coupled to the amplifier via a first switch matrix, and a second capacitor coupled to the amplifier via a second switch matrix, the first and second capacitors are operable in a four phase charge subtraction, the method comprising:

in a first phase, integrating a signal with the first capacitor and sampling the signal with the second capacitor;

in a second phase, integrating the signal with the second capacitor and sampling the signal with the first capacitor;

in a third phase, reversing the polarity of the first and second capacitors, integrating the signal with the first capacitor, and sampling the signal with the second capacitor; and

in a fourth phase, reversing the polarity of the first and second capacitors, integrating the signal with the second capacitor, and sampling the signal with the first capacitor.

16. A method for reducing noise in a detector circuit, the detector circuit includes a photodiode, an amplifier and a capacitor coupled to the amplifier via a switch matrix, the capacitor is operable in a multi-phase charge subtraction, the method comprising:

receiving an electronic signal corresponding to photon energy in a first phase;

accumulating charge from the electronic signal in the capacitor;

amplifying the electronic signal;

comparing the voltage of the electronic signal to a threshold voltage;

triggering the switch matrix to advance to a second phase when the voltage of the electronic signal passes the threshold voltage; and

reversing a polarity of the capacitor in the second phase using the switch matrix.