Paging cache optimization for virtual machine
View Patent ↗A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. For each guest physical page that is mapped to the real paging structures, paging means for handling a connection structure between the guest physical page and a real physical address of the guest physical page. A cache of connection structures represents cached paths to the real paging structures. Each path is described by guest paging structure descriptors and by tie descriptors. Each path includes a plurality of nodes connected by the tie descriptors. Each guest paging structure descriptor is in a node of at least one path. Each guest paging structure either points to other guest paging structures or to guest physical pages. Each guest paging structure descriptor represents guest paging structure information for mapping guest physical pages to the real paging structures.
1. A system for virtualizing a processor, comprising:
a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures;
a Virtual Machine (VM) running guest code and having at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space,
wherein at least some of the guest paging structures are mapped to the real paging structures;
for each guest physical page that is mapped to the real paging structures, means for handling a connection structure between the guest physical page and a real physical address of the guest physical page;
a cache of connection structures representing cached paths to the real paging structures;
each path being described by guest paging structure descriptors and by tie descriptors; and
each path comprising a plurality of nodes connected by the tie descriptors,
wherein each guest paging structure descriptor is in a node of at least one path,
wherein each guest paging structure either points to other guest paging structures or to guest physical pages, and
wherein each guest paging structure descriptor represents guest paging structure information for mapping guest physical pages to the real paging structures.
2. The system of claim 1 , wherein the guest paging structures and the real paging structures are organized into a hierarchy of layers.
3. The system of claim 2 , further comprising an additional layer that utilizes a CR3 cache for caching of paging translations for different values of CR3.
4. The system of claim 3 , wherein additional layers of the caching structure are added to describe different guest OS code working modes.
5. The system of claim 4 , wherein guest OS code working modes includes paged and non-paged modes.
6. The system of claim 4 , wherein each guest paging structure descriptor maintains links to at least one real paging structure to organize guest physical page mapping to the real paging structures.
7. The system of claim 6 , wherein guest OS paging mode and virtualization system paging mode are different.
8. The system of claim 2 , wherein the layers comprise a zeroth layer with pages, a first layer with page tables, and a second layer with page directories.
9. The system of claim 2 , wherein each layer has its own set of tie descriptors.
10. The system of claim 9 , further comprising a third layer with page directory page tables, and a fourth layer with PML4 tables.
11. The system of claim 2 , wherein the VM uses one of standard, PAE and EM64T addressing modes, and the VMM uses an addressing mode at least as high as the VM addressing mode.
12. The system of claim 2 , further comprising an additional higher layer for caching of multiple sets of paging caches.
13. The system of claim 1 , wherein the tie descriptors include pointers to other tie descriptors of the same layer.
14. The system of claim 1 , wherein the tie descriptors include pointers to paging elements of the next layer below.
15. The system of claim 1 , wherein the tie descriptors include pointers to paging elements of the next layer above.
16. A method for virtualizing a processor, comprising:
initiating a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures;
launching a Virtual Machine (VM) running guest code and having at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space,
wherein at least some of the guest paging structures are mapped to the real paging structures;
for each guest physical page that is mapped to the real paging structures, activating means for handling a connection structure between the guest physical page and a real physical address of the guest physical page;
generating a cache of connection structures representing cached paths to the real paging structures, each path being described by guest paging structure descriptors and by tie descriptors, and each path comprising a plurality of nodes connected by the tie descriptors,
wherein each guest paging structure descriptor is in a node of at least one path,
wherein each guest paging structure either points to other guest paging structures or to guest physical pages, and
wherein each guest paging structure descriptor represents guest paging structure information for mapping guest physical pages to the real paging structures.
17. The method of claim 16 , further comprising, when a physical page that is reflected in the guest paging structures is removed from mapping paths, using the tie descriptors to update the VMM paging structures.
18. The method of claim 16 , further comprising, when a physical page that is reflected in the guest paging structures is added to paging structures, using the tie descriptors to update the VMM paging structures.
19. A computer useable storage medium having computer program logic stored thereon for executing on a processor for virtualizing a processor, the computer program logic comprising:
computer program code means for initiating a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures;
computer program code means for launching a Virtual Machine (VM) running guest code and having at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space,
wherein at least some of the guest paging structures are mapped to the real paging structures;
for each guest physical page that is mapped to the real paging structures, computer program code means for activating and handling a connection structure between the guest physical page and a real physical address of the guest physical page;
computer program code means for generating a cache of connection structures representing cached paths to the real paging structures, each path being described by guest paging structure descriptors and by tie descriptors, and each path comprising a plurality of nodes connected by the tie descriptors,
wherein each guest paging structure descriptor is in a node of at least one path,
wherein each guest paging structure either points to other guest paging structures or to guest physical pages, and
wherein each guest paging structure descriptor represents guest paging structure information for mapping guest physical pages to the real paging structures.