Integrated voltage switching circuit
View Patent ↗An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.
1. An integrated circuit for operation at a specified maximum supply voltage, comprising:
first and second voltage supply terminals;
a first signal input for application of a regular input signal;
a second signal input;
an output;
a multiplexer with first and second inputs respectively coupled to the first and second signal inputs, for selectively switching either of the first and second signal inputs to the output under control of a selection signal;
a gate circuit providing the selection signal to the multiplexer;
clamping circuitry connected to limit the voltage at the first input of the multiplexer; and
control circuitry connected and configured to detect a voltage at the first signal input that exceeds a maximum supply voltage by a given amount and for driving an input of said gate circuit in response thereto.
2. The integrated circuit of claim 1 , wherein the clamping circuitry comprises a first resistor connected between the first signal input and the first input of the multiplexer, and a diode-connected first MOS transistor connected between the first input of the multiplexer and the first voltage supply terminal.
3. The integrated circuit of claim 2 , wherein the control circuitry comprises a second MOS transistor and a resistive divider, the channel of the second MOS transistor being connected in series with the resistive divider between the first input of the multiplexer and the second voltage supply terminal; the resistive divider having a node connected to the input of the gate circuit; and the second MOS transistor having a gate controlled by biasing circuitry.
4. The integrated circuit of claim 3 , wherein the biasing circuitry includes a diode-connected third MOS transistor connected between the first voltage supply terminal and the gate of the second MOS transistor, and a second resistor and fourth MOS transistor having a channel connected in series with the second resistor between the gate of the second MOS transistor and the second voltage supply terminal (DVSS) and a gate connected to the node of the resistive divider.
5. The integrated circuit of claim 4 , wherein the second MOS transistor is dimensioned substantially larger than the diode-connected first MOS transistor.
6. The integrated circuit of claim 3 , wherein the second MOS transistor is dimensioned substantially larger than the diode-connected first MOS transistor.
7. The integrated circuit of claim 6 , wherein the biasing circuitry includes a diode-connected second MOS transistor connected between the first voltage supply terminal and the gate of the first MOS transistor, and a resistor and third MOS transistor having a channel connected in series with the resistor between the gate of the first MOS transistor and the second voltage supply terminal (DVSS) and a gate connected to the node of the resistive divider.
8. The integrated circuit of claim 1 , wherein the control circuitry comprises a first MOS transistor and a resistive divider, the channel of the first MOS transistor being connected in series with the resistive divider between the first input of the multiplexer and the second voltage supply terminal; the resistive divider having a node connected to the input of the gate circuit; and the first MOS transistor having a gate controlled by biasing circuitry.