Method and apparatus for signal synchronizing
View Patent ↗A synchronizer and a method for synchronizing a communication signal are presented. The synchronizer comprises a first unit arranged for receiving a plurality of inputs. The plurality of inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal. The first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period. The synchronizer is further provided with a second unit. The second unit is configured for operating according to the indicative of destination clock period. The output of the first unit is provided to the second unit. The second unit is configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.
1. A synchronizer comprising:
a first unit arranged for receiving a plurality of inputs, the plurality of inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal, the first unit being configured for stretching the communication signal according to a ceil of a ratio of the indicative of the destination clock period and indicative of the source clock period; and
a second unit configured for operating according to the indicative of destination clock period and receiving output of the first unit, the second unit being configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.
2. A synchronizer comprising:
a first unit arranged for receiving a plurality of inputs, the plurality of inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal, the first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period; and
a second unit configured for operating according to the indicative of destination clock period and receiving output of the first unit, the second unit being configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain, wherein the second unit comprises:
a cascaded-synchronizer arranged for receiving input from the first unit and configured for adaptively adjusting the received input for converting it into a signal that is operable in the destination clock domain; and
a pulse generator coupled to the output of the cascaded-synchronizer, the pulse generator being configured for generating the synchronizer output signal in the destination clock domain substantially analogous to the communication signal in the source clock domain.
3. A method for synchronizing signals in a synchronizer comprising the steps of:
receiving a plurality of inputs, the inputs include at least an indicative of a source clock period of a source clock domain, an indicative of a destination clock period of a destination clock domain, and a communication signal;
stretching the communication signal according to a ceil of a ratio of the indicative of the destination clock period and indicative of the source clock period; and
obtaining a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.
4. The method as claimed in claim 3 , wherein the step of obtaining includes the steps of:
adaptively adjusting the received input for converting it into a signal that is operable in the destination clock domain; and
generating the synchronizer output signal in the destination clock domain substantially analogous to the communication signal in the source clock domain.
5. An integrated chip having a synchronizer, the synchronizer comprising:
a first unit arranged for receiving a plurality of inputs, the inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal, the first unit being configured for stretching the communication signal according to a ceil of a ratio of the indicative of the destination clock period and indicative of the source clock period; and
a second unit configured for operating according to the indicative of destination clock period and receiving output of the first unit, the second unit being configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.
6. An integrated chip having a synchronizer, the synchronizer comprising:
a first unit arranged for receiving a plurality of inputs, the inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal, the first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period; and
a second unit configured for operating according to the indicative of destination clock period and receiving output of the first unit, the second unit being configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain, wherein the second unit comprises:
a cascaded-synchronizer arranged for receiving input from the first unit and configured for adaptively adjusting the received input for converting it into a signal that is operable in the destination clock domain; and
a pulse generator coupled to the output of the cascaded-synchronizer, the pulse generator being configured for generating the synchronizer output signal in the destination clock domain substantially analogous to the communication signal in the source clock domain.
7. A method for manufacturing a synchronizer, the method comprising the steps of:
providing a first unit arranged for receiving a plurality of inputs, the inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal, the first unit being configured for stretching the communication signal according to a ceil of a ratio of the indicative of the destination clock period and indicative of the source clock period; and
providing a second unit configured for operating according to the indicative of destination clock period and receiving output of the first unit, the second unit being configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.
8. A method for manufacturing a synchronizer, the method comprising the steps of:
providing a first unit arranged for receiving a plurality of inputs, the inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal, the first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period; and
providing a second unit configured for operating according to the indicative of destination clock period and receiving output of the first unit, the second unit being configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain, wherein the step of providing the second unit comprises:
providing a cascaded-synchronizer arranged for receiving input from the first unit and configured for adaptively adjusting the received input for converting it into a signal that is operable in the destination clock domain; and
providing a pulse generator coupled to the output of the cascaded-synchronizer, the pulse generator being configured for generating the synchronizer output signal in the destination clock domain substantially analogous to the communication signal in the source clock domain.
9. A non-transitory computer readable storage medium operable with a computer system, the computer readable medium having stored thereon instructions operable with an architectural simulator environment supported by the computer system, the medium comprising instructions for synchronizing signals in a synchronizer by executing steps of:
receiving a plurality of inputs, the inputs include at least an indicative of a source clock period of a source clock domain, an indicative of a destination clock period of a destination clock domain, and a communication signal;
stretching the communication signal according to a ceil of a ratio of the indicative of the destination clock period and indicative of the source clock period; and
obtaining a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.
10. The non-transitory computer readable storage medium as claimed in claim 9 , wherein the step of obtaining includes the steps of:
adaptively adjusting the received input for converting it into a signal that is operable in the destination clock domain; and
generating the synchronizer output signal in the destination clock domain substantially analogous to the communication signal in the source clock domain.