Microelectromechanical system pressure sensor and method for making and using
View Patent ↗According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.
1. A method, comprising:
forming a conducting layer on a first wafer;
forming both an insulating layer on a substantially flat side of a second wafer, and a continuous conducting area disposed on or within only a portion of the second wafer, wherein only the insulating layer comprises a plurality of cavities abutting the second wafer continuous conducting area;
bonding a side of the conducting layer opposite the first wafer to a side of the insulating layer opposite the second wafer; and
removing at least a portion of the first wafer without removing at least a portion of the conducting layer such that the conducting layer forms a plurality of diaphragms that are electrically insulated with respect to one another, each diaphragm corresponding to one of the cavities and substantially parallel to the second wafer, and further such that the continuous conducting area forms a single fixed capacitor plate common to all cavities with corresponding diaphragms.
2. The method of claim 1 , wherein the second wafer is a lightly doped silicon wafer and said forming the continuous conducting area comprises:
creating a highly doped area in the second wafer via at least one of (i) diffusion or (ii) ion bombardment.
3. The method of claim 2 ,wherein forming an insulating layer comprises
forming a non-conducting protective layer over the highly doped area.
4. The method of claim 1 , wherein the first wafer comprises a lightly doped silicon wafer.
5. The method of claim 4 , wherein said forming the conducting layer comprises:
epitaxially growing a highly doped layer on the first wafer, wherein the surface of the highly doped layer opposite the first wafer is substantially smooth.
6. The method of claim 1 , wherein the first wafer comprises at least one of: (i) a silicon wafer or (ii) a silicon on insulator wafer.
7. The method of claim 6 , wherein said forming the insulating layer comprises:
creating an oxide layer on the second wafer via at least one of (i) growing the oxide layer and (ii) deposing the oxide layer, wherein the surface of the oxide layer opposite the second wafer is substantially smooth.
8. The method of claim 7 , wherein said forming the insulating layer further includes:
creating the plurality of cavities using a pattern mask and a potassium hydroxide wash.
9. The method of claim 1 , wherein at least one cavity is a reference cavity.
10. The method of claim 1 , wherein the plurality of diaphragms is associated with a microelectromechanical capacitive pressure sensor.