Granted Patent B2

US 7,779,284 · App. 11/678,440 · Granted Aug 17, 2010

Abstract

Claims (55)

1. A method of operating a processor subsystem, comprising:

masking interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem;

setting a boot vector for the processor of the processor subsystem, the boot vector providing an address associated with a saved processor state;

saving a current state of the processor to provide the saved processor state;

determining whether one or more first masked interrupts occurred during the saving of the current state of the processor;

stopping the processor that is to be powered-down when the one or more first masked interrupts did not occur during the saving of the current state of the processor;

determining whether one or more second masked interrupts occurred following the saving of the current state of the processor; and

powering-down the processor when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

2. The method of claim 1 , further comprising:

receiving an indication that the processor is to be powered-down.

3. The method of claim 1 , further comprising:

unmasking the interrupts to the processor subsystem when the one or more first masked interrupts occurred during the saving of the current state of the processor; and

servicing the one or more first masked interrupts with the processor when the one or more first masked interrupts occurred during the saving of the current state of the processor.

4. The method of claim 1 , further comprising:

unmasking the interrupts to the processor subsystem when the one or more second masked interrupts occurred following the saving of the current state of the processor;

generating a wake-up signal to the processor when the one or more second masked interrupts occurred following the saving of the current state of the processor; and

servicing the one or more second masked interrupts with the processor when the one or more second masked interrupts occurred following the saving of the current state of the processor.

5. The method of claim 1 , further comprising:

monitoring for one or more post power-down interrupts;

unmasking the interrupts to the processor subsystem based on occurrence of the one or more post power-down interrupts;

generating a wake-up signal to the processor based on occurrence of the one or more post power-down interrupts;

powering-up the processor based on occurrence of the one or more post power-down interrupts;

restoring a state of the processor with the saved processor state based on occurrence of the one or more post power-down interrupts; and

servicing the one or more post power-down interrupts with the processor.

6. The method of claim 1 , further comprising:

determining whether one or more third masked interrupts occurred during the powering-down of the processor;

unmasking the interrupts to the processor subsystem based on occurrence of the one or more third masked interrupts;

generating a wake-up signal to the processor based on occurrence of the one or more third masked interrupts;

powering-up the processor based on occurrence of the one or more third masked interrupts;

restoring a state of the processor with the saved processor state based on occurrence of the one or more third masked interrupts; and

servicing the one or more third masked interrupts with the processor.

7. The method of claim 1 , wherein the setting further comprises:

enabling and programming the boot vector for the processor of the processor subsystem.

8. A system, comprising:

a processor subsystem including a processor;

a power control module coupled between the processor subsystem and an interrupt source, wherein the power control module is configured to mask interrupts to the processor subsystem during a power-down sequence of the processor of the processor subsystem; and

wherein the system is further configured to determine whether one or more first masked interrupts occurred during the saving of the current state of the processor and control the power control module to unmask the interrupts to the processor subsystem when the one or more first masked interrupts occurred during the saving of the current state of the processor, and wherein the processor is further configured to service the one or more first masked interrupts when the one or more first masked interrupts occurred during the saving of the current state of the processor.

9. The system of claim 8 , wherein the power control module is further configured to store a boot vector for the processor of the processor subsystem, the boot vector providing an address associated with a saved processor state.

10. The system of claim 8 , the processor subsystem further comprising:

a powered-on memory, wherein the powered-on memory is configured to store a current state of the processor to provide a saved processor state during and following the power-down sequence.

11. A system comprising:

a processor subsystem including a processor;

a power control module coupled between the processor subsystem and an interrupt source, wherein the power control module is configured to mask interrupts to the processor subsystem during a power-down sequence of the processor of the processor subsystem; and

wherein the processor is further configured to stop when one or more first masked interrupts did not occur during the saving of the current state of the processor, and wherein the power control module is further configured to determine whether one or more second masked interrupts occurred following the saving of the current state of the processor and power-down the processor when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

12. The system of claim 11 , wherein the power control module is further configured to unmask the interrupts to the processor subsystem when the one or more second masked interrupts occurred following the saving of the current state of the processor and generate a wake-up signal to the processor when the one or more second masked interrupts occurred following the saving of the current state of the processor, and wherein the processor is further configured to service the one or more second masked interrupts when the one or more second masked interrupts occurred following the saving of the current state of the processor.

13. The system of claim 11 , wherein the power control module is further configured to determine whether one or more third masked interrupts occurred during the powering-down of the processor and monitor for one or more post power-down interrupts when the one or more third masked interrupts did not occur during the powering-down of the processor.

14. The system of claim 13 , wherein the power control module is further configured to unmask the interrupts to the processor subsystem based on occurrence of the one or more post power-down interrupts, generate a wake-up signal to the processor based on occurrence of the one or more post power-down interrupts and power-up the processor based on occurrence of the one or more post power-down interrupts, and wherein the processor is further configured to restore a state of the processor with the saved processor state based on occurrence of the one or more post power-down interrupts and service the one or more post power-down interrupts.

15. The system of claim 11 , wherein the power control module is further configured to determine whether one or more third masked interrupts occurred during the powering-down of the processor, unmask the interrupts to the processor subsystem based on occurrence of the one or more third masked interrupts, generate a wake-up signal to the processor based on occurrence of the one or more third masked interrupts, power-up the processor based on occurrence of the one or more third masked interrupts and set a restore of a state of the processor with the saved processor state based on occurrence of the one or more third masked interrupts, and wherein the processor is further configured to service the one or more third masked interrupts with the processor.

16. A power control module coupled between a processor subsystem and an interrupt source, the power control module comprising:

a first module configured to mask and detect interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem;

a second module configured to store a boot vector for the processor of the processor subsystem, the boot vector providing an address associated with a saved processor state of the processors;

wherein the power control module is further configured to determine whether one or more second masked interrupts occurred following saving of the saved processor state and power-down the processor when the one or more second masked interrupts did not occur following the saving of the saved processor state; and

wherein the power control module is further configured to unmask the interrupts to the processor subsystem when the one or more second masked interrupts occurred following the saving of the saved processor state and generate a wake-up signal to the processor when the one or more second masked interrupts occurred following the saving of the saved processor state.

17. The power control module of claim 16 , wherein the power control module is further configured to determine whether one or more second masked interrupts occurred following saving of the saved processor state and power-down the processor when the one or more second masked interrupts did not occur following the saving of the saved processor state.

18. The power control module of claim 17 , wherein the power control module is further configured to unmask the interrupts to the processor subsystem when the one or more second masked interrupts occurred following the saving of the saved processor state and generate a wake-up signal to the processor when the one or more second masked interrupts occurred following the saving of the saved processor state.

Assignments (8)