Thin film transistor array panel and manufacturing method thereof
View Patent ↗Gate lines are formed on a substrate. A gate insulating layer, a semiconductor layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited, and the upper film and the lower film are patterned to form data lines and drain electrodes. A photoresist is formed, and the upper film is patterned using the photoresist as an etch mask to expose contact portions of the lower film of the drain electrodes. Exposed portions of the extrinsic a-Si layer and the intrinsic a-Si layer are removed, and then the photoresist and underlying portions of the extrinsic a-Si layer are removed. A passivation layer is formed and patterned along with the gate insulating layer to form contact holes exposing the contact portions of the lower film, and pixel electrodes are formed to contact the contact portions.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate conductive layer on an insulating substrate;
forming a gate insulating layer on the gate conductive layer;
forming a semiconductor layer on the gate insulating layer;
forming a data conductive layer at least in part on the semiconductor layer, the data conductive layer comprising a data line, a source electrode coupled to the data line and a drain electrode separated from the source electrode, and the data conductive layer also comprising an upper conductive film and a lower conductive film;
forming a passivation layer on the data conductive layer and the semiconductor layer, a portion of the passivation layer directly contacting the lower conductive film; and
forming a pixel conductive layer contacting the lower conductive film,
wherein the formation of the semiconductor layer and the data conductive layer comprises:
depositing an amorphous silicon layer on the gate insulating layer;
forming the data conductive layer on the amorphous silicon layer;
coating a photoresist on the upper conductive film and the amorphous silicon layer;
removing a first portion of the upper conductive film, the first portion being exposed out of the photoresist; and
forming the semiconductor layer comprising the amorphous silicon layer by removing portions of the amorphous silicon layer exposed out of the data conductive layer and the photoresist.
2. The method of claim 1 , wherein the lower conductive film comprises a barrier metal, and the upper conductive film comprises Al or Al alloy.
3. The thin film transistor array panel of claim 1 , further comprising:
forming an ohmic contact between the semiconductor layer and the data conductive layer.
4. The method of claim 1 , wherein the first portion of the upper conductive film is not covered with the photoresist, the semiconductor layer includes a channel portion located between the source electrode and the drain electrode, and the photoresist covers the channel portion.
5. The method of claim 4 , wherein the amorphous silicon layer includes an intrinsic amorphous silicon film and an extrinsic amorphous silicon film on the intrinsic amorphous silicon film, and further comprising:
removing the photoresist after the formation of the semiconductor layer; and
removing portions of the extrinsic amorphous silicon film exposed out of the data conductive layer.
6. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate conductive layer on an insulating substrate;
forming a gate insulating layer on the gate conductive layer;
forming a semiconductor layer on the gate insulating layer;
forming a data conductive layer at least in part on the semiconductor layer, the data conductive layer comprising a data line, a source electrode coupled to the data line and a drain electrode separated from the source electrode, and the data conductive layer also comprising an upper conductive film and a lower conductive film;
forming a passivation layer on the data conductive layer and the semiconductor layer, a portion of the passivation layer directly contacting the lower conductive film; and
forming a pixel conductive layer contacting the lower conductive film
wherein the formation of the data conductive layer comprises leaving an island-like portion of the upper conductive film on the lower conductive film; and
further comprising removing the island-like portion of the upper conductive film by blanket etch before the formation of the pixel conductive layer.
7. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on an insulating substrate;
forming a gate insulating layer on the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a data conductive layer at least in part on the semiconductor layer, the data conductive layer comprising a data line, a source electrode coupled to the data line and a drain electrode separated from the source electrode, and the data conductive layer also comprising an upper film and a lower film;
forming a passivation layer on the data conductive layer and the semiconductor layer, a portion of the passivation layer directly contacting the lower film; and
forming a pixel conductive layer contacting the lower film,
wherein the formation of the semiconductor layer and the data conductive layer comprises:
depositing an amorphous silicon layer on the gate insulating layer;
forming the data conductive layer on the amorphous silicon layer;
forming the photoresist on the upper film and the amorphous silicon layer;
removing the uncovered portion of the upper film; and
forming the semiconductor layer including the amorphous silicon layer by removing portions of the amorphous silicon layer exposed out of the data conductive layer and the photoresist.
8. The method of claim 7 , further comprising:
removing a portion of the upper film to expose a portion of the lower film.
9. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on an insulating substrate;
forming a gate insulating layer on the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a data conductive layer at least in part on the semiconductor layer, the data conductive layer comprising a data line, a source electrode coupled to the data line and a drain electrode separated from the source electrode, and the data conductive layer also comprising an upper film and a lower film;
forming a passivation layer on the data conductive layer and the semiconductor layer, a portion of the passivation layer directly contacting the lower film; and
forming a pixel conductive layer contacting the lower film
wherein the formation of the data conductive layer comprises leaving an island-like portion of the upper film on the lower film; and
further comprising removing the island-like portion of the upper film by blanket etch before the formation of the pixel conductive layer.
10. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on an insulating substrate;
forming successively a gate insulating layer on the gate line, a semiconductor layer on the gate insulating layer, a first data conductive layer on the gate insulating layer, a second data conductive layer on the first data conductive layer, and a first photo resist layer on the second conductive layer;
patterning successively the first photo resist layer, the second data conductive layer, and the first data conductive layer;
patterning the semiconductor layer;
forming a passivation layer on the second data conductive layer and the semiconductor layer; and
forming a pixel conductive layer on the passivation layer.
11. The method of claim 10 , further comprising:
removing the first photo resist layer after patterning the first data conductive layer;
forming a second photo resist layer on the second data conductive layer and the semiconductor layer;
patterning the second photo resist layer exposing a portion of the semiconductor layer and a portion of the second data conductive layer; and
removing the exposed portion of the semiconductor layer and the second data conductive layer.
12. The method of claim 11 ,
wherein the pattering of the first and second data conductive layer comprises a data line, a source electrode coupled to the data line, and a drain electrode separated from the source electrode.
13. The method of claim 12 , further comprising:
removing the second photo resist pattern;
removing a portion of the semiconductor layer between the source electrode and the drain electrode after removing the second photo resist pattern.
14. The method of claim 13 ,
wherein the passivation layer contacts directly the first data conductive layer.
15. The method of claim 14 ,
wherein the semiconductor layer comprises an intrinsic semiconductor and an extrinsic semiconductor.
16. The method of claim 15 ,
wherein the intrinsic semiconductor is silicon.
17. The method of claim 10 ,
wherein the passivation layer contacts directly the first data conductive layer.
18. The method of claim 10 ,
wherein the semiconductor layer comprises an intrinsic semiconductor and an extrinsic semiconductor.