Ultra low temperature fixed X7R and BX dielectric ceramic composition and method of making
View Patent ↗Multilayer ceramic chip capacitors which satisfy X7R and BX requirements and which are compatible with silver-palladium internal electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers comprise a lead-free and cadmium-free barium titanate base material doped with other metal oxides such oxides of zinc, boron, bismuth, cerium, tungsten, copper, manganese, neodymium, niobium, silver, barium, silicon and nickel in various combinations. The dielectric ceramic materials herein can be sintered together (fired) at less than 1000° C. with an inner electrode having more than 80 wt % Ag and less than 20 wt % Pd to form a multilayer ceramic capacitor (MLCC).
1. A lead-free and cadmium-free ceramic dielectric composition for multilayer ceramic capacitor manufacturing comprising:
a. about 85 to about 98 wt % BaTiO 3 ,
b. about 0.3 to about 2.5 wt % ZnO,
c. about 0.05 to about 1 wt % B 2 O 3 ,
d. about 1 to about 8 wt % Bi 2 O 3 ,
e. about 0.05 to about 1.5 wt % CeO 2 ,
f. about 0.01 to about 2 wt % WO 3 ,
g. about 0.01 to about 0.5 wt % CuO, and
h. about 0.01 to about 0.5 wt % MnO.
2. The composition of claim 1 , comprising:
a. about 90 to about 97 wt % BaTiO 3 ,
b. about 0.5 to about 2 wt % ZnO,
c. about 0.1 to about 0.8 wt % B 2 O 3 ,
d. about 1.5 to about 6 wt % Bi 2 O 3 ,
e. about 0.1 to about 1 wt % CeO 2 ,
f. about 0.2 to about 1.7 wt % WO 3 ,
g. about 0.05 to about 0.35 wt % CuO, and
h. about 0.03 to about 0.3 wt % MnO.
3. The composition of claim 1 , comprising:
a. about 90.5 to about 96.5 wt % BaTiO 3 ,
b. about 0.7 to about 1.7 wt % ZnO,
c. about 0.15 to about 0.4 wt % B 2 O 3 ,
d. about 2 to about 5 wt % Bi 2 O 3 ,
e. about 0.2 to about 0.7 wt % CeO 2 ,
f. about 0.4 to about 1.4 wt % WO 3 ,
g. about 0.05 to about 0.25 wt % CuO, and
h. about 0.04 to about 0.2 wt % MnO.
4. The composition of claim 1 , further comprising Ag 2 O, wherein the content of Ag 2 O does not exceed about 2 wt %.
5. The composition of claim 2 , further comprising at least one of BaO and SiO 2 , wherein the content of BaO does not exceed about 1 wt % and the content of SiO 2 does not exceed about 0.5 wt %.
6. A lead-free and cadmium-free ceramic dielectric composition for multilayer ceramic capacitor manufacturing comprising:
a. about 85 to about 98 wt % BaTiO 3 ,
b. about 0.2 to about 2 wt % ZnO,
c. about 0.1 to about 1 wt % B 2 O 3 ,
d. about 1 to about 4 wt % Bi 2 O 3 ,
e. about 0.1 to about 1 wt % CeO 2 ,
f. about 0.1 to about 1.5 wt % WO 3 ,
g. about 0.05 to about 0.5 wt % Nd 2 O 3 ,
h. about 0.01 to about 0.5 wt % TiO 2 ,
i. about 0.01 to about 0.5 wt % CuO, and
j. about 0.01 to about 0.5 wt % MnO.
7. The composition of claim 6 , comprising:
a. about 92 to about 97 wt % BaTiO 3 ,
b. about 0.5 to about 1.5 wt % ZnO,
c. about 0.15 to about 0.7 wt % B 2 O 3 ,
d. about 1.7 to about 3.3 wt % Bi 2 O 3 ,
e. about 0.2 to about 0.7 wt % CeO 2 ,
f. about 0.4 to about 1.2 wt % WO 3 ,
g. about 0.05 to about 0.3 wt % Nd 2 O 3 ,
h. about 0.05 to about 0.3 wt % TiO 2 ,
i. about 0.015 to about 0.07 wt % CuO, and
j. about 0.02 to about 0.07 wt % MnO.
8. The composition of claim 6 comprising:
a. about 93.5 to about 96.5 wt % BaTiO 3 ,
b. about 0.6 to about 1.2 wt % ZnO,
c. about 0.2 to about 0.5 wt % B 2 O 3 ,
d. about 2 to about 3 wt % Bi 2 O 3 ,
e. about 0.25 to about 0.6 wt % CeO 2 ,
f. about 0.5 to about 1 wt % WO 3 ,
g. about 0.1 to about 0.25 wt % Nd 2 O 3 ,
h. about 0.08 to about 0.2 wt % TiO 2 ,
i. about 0.02 to about 0.06 wt % CuO, and
j. about 0.03 to about 0.06 wt % MnO.
9. The composition of claim 6 further comprising Ag 2 O, wherein the content of Ag 2 O does not exceed about 2.5 wt %.
10. The composition of claim 7 further comprising about 0.05 to about 0.5 wt % Ag 2 O.
11. A lead-free and cadmium-free ceramic dielectric composition for multilayer ceramic capacitor manufacturing comprising:
a. about 85 to about 98 wt % BaTiO 3 ,
b. about 0.5 to about 2 wt % ZnO,
c. about 0.1 to about 1.5 wt % B 2 O 3 ,
d. about 0.05 to about 0.5 wt % NiO,
e. about 0.1 to about 1 wt % Nb 2 O 5 ,
f. about 0.5 to about 3 wt % Bi 2 O 3 ,
g. about 0.1 to about 5 wt % CeO 2 ,
h. about 0.2 to about 2 wt % WO 3 ,
i. about 0.01 to about 0.5 wt % CuO,
j. about 0.05 to about 0.5 wt % BaSO 4 , and
k. about 0.01 to about 0.5 wt % MnO.
12. The composition of claim 11 , comprising:
a. about 92 to about 96 wt % BaTiO 3 ,
b. about 1 to about 2 wt % ZnO,
c. about 0.2 to about 0.6 wt % B 2 O 3 ,
d. about 0.1 to about 0.4 wt % NiO,
e. about 0.2 to about 0.7 wt % Nb 2 O 5 ,
f. about 1.5 to about 2.5 wt % Bi 2 O 3 ,
g. about 0.2 to about 0.45 wt % CeO 2 ,
h. about 0.3 to about 1 wt % WO 3 ,
i. about 0.02 to about 0.4 wt % CuO,
j. about 0.1 to about 0.3 wt % BaSO 4 , and
k. about 0.03 to about 0.35 wt % MnO.
13. The composition of claim 11 , comprising:
a. about 93 to about 95 wt % BaTiO 3 ,
b. about 1 to about 1.5 wt % ZnO,
c. about 0.3 to about 0.5 wt % B 2 O 3 ,
d. about 0.15 to about 0.35 wt % NiO,
e. about 0.3 to about 0.5 wt % Nb 2 O 5 ,
f. about 1.7 to about 2.3 wt % Bi 2 O 3 ,
g. about 0.25 to about 0.35 wt % CeO 2 ,
h. about 0.5 to about 0.8 wt % WO 3 ,
i. about 0.02 to about 0.2 wt % CuO,
j. about 0.12 to about 0.25 wt % BaSO 4 , and
k. about 0.04 to about 0.2 wt % MnO.
14. The composition of claim 11 , further comprising Ag 2 O, wherein the content of Ag 2 O does not exceed about 0.5 wt %.
15. The composition of claim 12 , further comprising 0.1 to about 0.2 wt % Ag 2 O.
16. A multilayer ceramic chip capacitor having a dielectric constant greater than about 2000, a dissipation factor less than about 2%, and meeting X7R and BX standards comprising a fired collection of alternately stacked:
a. layers of the dielectric composition of claim 1 and
b. layers of an internal electrode material comprising a metal portion selected from the group consisting of silver, palladium, mixtures thereof and alloys thereof.
17. The capacitor of claim 16 wherein the metal portion comprises at least 80 wt % silver, and less than 20 wt % palladium.
18. A multilayer ceramic chip capacitor having a dielectric constant greater than about 2000, a dissipation factor less than about 2%, meeting X7R and BX standards comprising a fired collection of alternately stacked:
a. layers of the dielectric composition of claim 6 and
b. layers of an internal electrode material comprising a metal portion selected from the group consisting of silver, palladium, mixtures thereof and alloys thereof.
19. The capacitor of claim 18 wherein the metal portion comprises at least 80 wt % silver, and less than 20 wt % palladium.
20. A multilayer ceramic chip capacitor having a dielectric constant greater than about 2000, a dissipation factor less than about 2%, meeting X7R and BX standards comprising a fired collection of alternately stacked:
a. layers of the dielectric composition of claim 11 and
b. layers of an internal electrode material comprising a metal portion selected from the group consisting of silver, palladium, mixtures thereof and alloys thereof.
21. The capacitor of claim 20 wherein the metal portion comprises at least 80 wt % silver, and less than 20 wt % palladium.
22. A method of forming an electronic component comprising:
a. alternately applying
i. layers of the dielectric composition of claim 1 and
ii. layers of an internal electrode material comprising a metal portion selected from the group consisting of silver, palladium, mixtures thereof and alloys thereof, onto a substrate to form a stack, and
b. firing the stack at a temperature not exceeding 1000° C. such that the dielectric fuses and the metal sinters.
23. The method of claim 22 wherein the metal portion comprises at least 80 wt % silver and less than 20 wt % palladium.
24. A method of forming an electronic component comprising:
a. alternately applying
i. layers of the dielectric composition of claim 6 and
ii. layers of an internal electrode material comprising a metal portion selected from the group consisting of silver, palladium, mixtures thereof and alloys thereof, onto a substrate to form a stack, and
b. firing the stack at a temperature not exceeding 1000° C. such that the dielectric fuses and the metal sinters.
25. The method of claim 24 wherein the metal portion comprises at least 80 wt % silver and less than 20 wt % palladium.