IP Library Granted Patent US 7,858,466
Granted Patent B2
US 7,858,466 · App. 11/682,621 · Granted Dec 28, 2010

Different-voltage device manufactured by a CMOS compatible process and high-voltage device used in the different-voltage device

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Quick Facts
Patent No.
US 7,858,466
App. No.
11/682,621
Granted
Dec 28, 2010
Kind
B2
Abstract

A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Claims (14)

1. A different-voltage device, manufactured by a process compatible with a CMOS process, the different-voltage device comprising:

a high-voltage device in a high-voltage region and a low-voltage device in a low-voltage region, wherein the high-voltage device is manufactured with a low-voltage device process, and two additional masks are further added to manufacture the high-voltage device, and a low-voltage gate oxide layer is disposed directly on a high-voltage gate oxide layer in the high voltage region and on a surface of a substrate in the low-voltage region,

wherein the low-voltage gate oxide layer provided on the high-voltage gate oxide layer together with the high-voltage gate oxide layer thereunder serve as a high-voltage gate oxide member of the high-voltage device, and the low-voltage gate oxide layer provided on the surface of the low-voltage device serves as a low-voltage gate oxide member of the low-voltage device,

wherein the high-voltage gate oxide member of the high-voltage device has a height higher than the low-voltage gate oxide member of the low-voltage device,

wherein the depth of a high-voltage well of the high-voltage device is deeper than the depth of a low-voltage well of the low-voltage device,

wherein the high-voltage gate oxide layer in the high-voltage region is higher than the surface of the substrate in the low-voltage region, and

wherein the high-voltage region and the low-voltage region are isolated by a field oxide and an isolation well thereunder, and the isolation well is directly connected between the high-voltage well of the high-voltage device and the low-voltage well of the low-voltage device, types of the low-voltage well and the high-voltage well are complementary.

2. The different-voltage device as claimed in claim 1 , wherein the high-voltage device and the low-voltage device are isolated from each other.

3. A high-voltage device used in a different-voltage device which is manufactured by a process compatible with a CMOS process, wherein a high-voltage device is manufactured with a process of a low-voltage device, two additional masks are further added to manufacture the high-voltage device, and a low-voltage gate oxide layer is disposed directly on a high-voltage gate oxide layer in a high voltage region and on a surface of a substrate in a low-voltage region,

wherein the low-voltage gate oxide layer provided on the high-voltage gate oxide layer together with the high-voltage gate oxide layer thereunder serve as a high-voltage gate oxide member of the high-voltage device, and the low-voltage gate oxide layer provided on the surface of the low-voltage device serves as a low-voltage gate oxide member of the low-voltage device,

wherein the high-voltage gate oxide member of the high-voltage device has a height higher than the low-voltage gate oxide member of the low-voltage device,

wherein the depth of a high-voltage well of the high voltage device is deeper than the depth of a low-voltage well of the low-voltage device,

wherein the high-voltage gate oxide layer in the high-voltage region is higher than the surface of the substrate in the low-voltage region, and

wherein the high-voltage region and the low-voltage region are isolated by a field oxide and an isolation well thereunder, and the isolation well is directly connected between the high-voltage well of the high-voltage device and the low-voltage well of the low-voltage device, types of the low-voltage well and the high-voltage well are complementary.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2017
From: HUANG, CHIH-FENG; YANG, TA-YUNG; LIN, JENN-YU G.; CHIEN, TUO-HSIN
To: SYSTEM GENERAL CORP.
Reel/Frame 041378/0131 →