Low overhead access to shared on-chip hardware accelerator with memory-based interfaces
In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.
1. A method comprising:
requesting access to a hardware accelerator by a user-privileged thread;
granting access to the hardware accelerator to the user-privileged thread by a higher-privileged thread responsive to the requesting;
communicating one or more commands to the hardware accelerator by the user-privileged thread responsive to the granting and without intervention by higher-privileged threads to perform the communicating, including without intervention by the higher-privileged thread that granted access to the hardware accelerator to the user-privileged thread, wherein the one or more commands cause the hardware accelerator to perform one or more tasks;
checking a permission value correspond to the user-privileged thread, the checking performed by the user-privileged thread to ensure that the user-privileged thread retains permission to access the hardware accelerator, wherein the higher-privileged thread updates the permission value to revoke access by the user-privileged thread to the hardware accelerator; and
communicating one or more additional commands to the hardware accelerator from the user-privileged thread responsive to detecting that the user-privileged thread retains permission to access the hardware accelerator.
2. The method as recited in claim 1 wherein the communicating comprises:
writing the one or more commands to a memory queue in user-privileged memory; and
reading the commands from the memory queue by the accelerator.
3. The method as recited in claim 2 further comprising writing a status to the memory queue by the hardware accelerator responsive to completing the one or more tasks.
4. The method as recited in claim 1 wherein the communicating comprises storing one or more commands to a queue in the hardware accelerator, and wherein the storing comprises executing a store instruction having a first virtual address and a data operand, and wherein the data operand comprises a second virtual address, and wherein the communicating further comprises translating the first virtual address to a first physical address and the second virtual address to a second physical address.
5. The method as recited in claim 1 wherein the granting comprises providing an identifier for the user-privileged thread to the accelerator, and the method further comprising the accelerator validating the one or more commands with the identifier.
6. The method as recited in claim 5 wherein the granting further comprises providing one or more physical page addresses to the accelerator, the one or more physical page addresses identifying one or more physical pages in user-privileged memory that store input data for the accelerator or to which the accelerator is to write results.
7. The method as recited in claim 6 wherein the granting further comprises supplying one or more virtual page addresses to the user-privileged thread, each of the one or more virtual page addresses mapped to one of the one or more physical page addresses via translation data.
8. The method as recited in claim 1 wherein the granting comprises:
determining that access to the hardware accelerator has been granted to another thread; and
revoking the other thread's access to the hardware accelerator responsive to the determining.
9. The method as recited in claim 1 wherein the higher-privileged thread is part of an operating system.
10. The method as recited in claim 1 wherein the higher-privileged thread is part of a Hypervisor.
11. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed as a user-privileged thread by a computer:
request access to a hardware accelerator from a higher-privileged thread;
communicate one or more commands to the hardware accelerator responsive to receiving a grant of access to the hardware accelerator without intervention by higher-privileged threads to perform the communication, wherein the one or more commands cause the hardware accelerator to perform one or more tasks, and wherein the one or more commands include an identifier that uniquely identifies the user-privileged thread, wherein the user-privileged thread, when executed, includes the identifier with the one or more commands provided to the hardware accelerator to validate the one or more commands, wherein the identifier is provided to the hardware accelerator by the higher-privileged thread in response to the grant of the access to the hardware accelerator to the user-privileged thread; and
check a permission value corresponding to the user-privileged thread to ensure that the user-privileged thread retains permission to access the hardware accelerator prior to communicating the one or more commands, wherein the higher-privileged thread updates the permission value to revoke access by the user-privileged thread to the hardware accelerator, and wherein the one or more commands are transmitted in response to the user-privileged thread retaining access to the hardware accelerator as indicated by the permission value.
12. The non-transitory computer accessible storage medium as recited in claim 11 wherein the instructions which communicate the one or more commands comprise instructions which, when executed, write the one or more commands to a memory queue in user-privileged memory.
13. The non-transitory computer accessible storage medium as recited in claim 11 wherein the instructions which communicate the one or more commands comprise a store instruction having a first virtual address and a data operand, and wherein the data operand comprises a second virtual address.
14. The computer non-transitory computer accessible storage medium as recited in claim 11 wherein the instructions, when executed, read a status provided by the hardware accelerator to determine that the one or more tasks are complete.
15. The non-transitory computer accessible storage medium as recited in claim 14 wherein the instructions, when executed, perform error processing if the status indicates an error.
16. The non-transitory computer accessible storage medium as recited in claim 14 wherein the instructions, when executed, read results of the one or more tasks from memory responsive to the status indicating no error.
17. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed as a higher-privileged thread by a computer:
receive a request to access a hardware accelerator from a user-privileged thread;
grant access to the hardware accelerator to the user-privileged thread responsive to the request, the grant including data permitting the user-privileged thread and the hardware accelerator to communicate without intervention by higher-privileged threads to perform the communication, including without intervention by the higher-privileged thread that granted access to the hardware accelerator to the user-privileged thread;
update a permission value corresponding to the user-privileged thread to indicate that the user-privileged thread has permission to access the hardware accelerator responsive to granting access to the user privileged thread;
determine that access by the user-privileged thread to the hardware accelerator is to be revoked subsequent to granting access to the user-privileged thread; and update the permission value corresponding to the user-privileged thread to indicate that the user-privileged thread is not permitted to access the hardware accelerator responsive to determining that the access by the user-privileged thread is to be revoked.
18. The non-transitory computer accessible storage medium as recited in claim 17 wherein the data comprises one or more physical page addresses provided to the accelerator, the one or more physical page addresses identifying one or more physical pages in user-privileged memory that store input data for the accelerator or to which the accelerator is to write results.
19. The non-transitory computer accessible storage medium as recited in claim 18 wherein the data further comprises one or more virtual page addresses provided to the user-privileged thread, each of the one or more virtual page addresses mapped to one of the one or more physical page addresses via translation data.
20. The non-transitory computer accessible storage medium as recited in claim 17 wherein the instructions which, when executed, grant access comprise instructions which, when executed:
determine that access to the hardware accelerator has been granted to another thread; and
revoke the other thread's access to the hardware accelerator responsive to the determining.