Compact low voltage low noise amplifier
View Patent ↗An apparatus comprising a first stage and a second stage. The first stage generally comprises a first transistor configured as a common-emitter amplifier. The second stage generally comprises a second and third transistor configured as a low voltage Darlington transistor pair. The first stage may be directly coupled to the second stage. The second transistor generally comprises a field effect (FET) input transistor. The third transistor generally comprises a bipolar output transistor. In one example, the apparatus may comprise a 2-stage RF amplifier operating from DC to microwave frequencies.
1. An apparatus comprising:
a first stage comprising a first transistor configured as a common-emitter amplifier;
a second stage comprising a second and third transistor configured as a low voltage Darlington transistor pair, wherein (i) said first stage is directly coupled to said second stage, (ii)
said second transistor comprises a field effect (FET) input transistor, and (iii) said third transistor comprises a bipolar output transistor; and
a feedback resistor coupled between a base of said common-emitter amplifier and a source of said FET input transistor.
2. The apparatus according to claim 1 , wherein said first transistor comprises a bipolar transistor.
3. The apparatus according to claim 1 , wherein said apparatus comprises a 2-stage RF amplifier operating from DC to microwave frequencies.
4. The apparatus according to claim 1 , wherein said FET input transistor is configured to provide a near zero gate to source voltage during DC operation.
5. An apparatus comprising:
a first stage comprising a first transistor configured as a common-emitter amplifier;
a second stage comprising a second and third transistor configured as a low voltage Darlington transistor pair, wherein (i) said first stage is directly coupled to said second stage, (ii)
said second transistor comprises a field effect (FET) input transistor, and (iii) said third transistor comprises a bipolar output transistor; and
an inductor coupled to an emitter of said third transistor, wherein said FET input transistor is configured to provide a gate to source voltage of less than 200 mV during DC operation.
6. The apparatus according to claim 1 , wherein said FET input transistor comprises a zero-threshold MOSFET transistor configured to provide zero or near-zero gate to source voltage operating characteristics.
7. The apparatus according to claim 1 , wherein said FET input transistor comprises a depletion mode MESFET or HEMT device for providing zero or near-zero gate to source voltage operating characteristics.
8. The apparatus according to claim 1 , further comprising:
a feedback resistor coupled from a collector of the common-emitter input stage to a drain of the FET input transistor of the low voltage Darlington transistor pair.
9. An apparatus comprising:
a first stage comprising a first transistor configured as a common-emitter amplifier;
a second stage comprising a second and third transistor configured as a low voltage Darlington transistor pair, wherein (i) said first stage is directly coupled to said second stage, (ii)
said second transistor comprises a field effect (FET) input transistor, and (iii) said third transistor comprises a bipolar output transistor; and
an inductor (i) coupled to an emitter of said first stage and (ii) configured to provide low noise matching.
10. The apparatus according to claim 1 , wherein said apparatus is configured to operate using a supply voltage as low as a base to emitter voltage of the FET input transistor.
11. The apparatus according to claim 1 , wherein said apparatus is configured to achieve low broadband noise.
12. The apparatus according to claim 1 , wherein said amplifier is fabricated using BiCMOS technology.
13. The apparatus according to claim 1 , wherein said amplifier is fabricated using FET-HBT compound semiconductor technology.
14. The apparatus according to claim 1 , wherein said apparatus is monolithically integrated.
15. The apparatus according to claim 1 , wherein said amplifier employs a feedback field effect transistor (FET) (i) in series with a collector of the common-emitter bipolar transistor and (ii) configured to provide power down control.
16. The apparatus according to claim 15 , wherein said feedback FET comprises a zero or near-zero threshold FET configured to provide an amplifier power down.
17. The apparatus according to claim 15 , wherein said feedback FET comprises a depletion mode HEMT device.
18. The apparatus according to claim 15 , wherein said FET transistors and Bipolar transistors are fabricated using GaAs or other III-V compound semiconductor technology.
19. The apparatus according to claim 18 , further comprising:
an E-mode FET configured (i) in series with a drain of first said FET input transistor and (ii) to provide power down control.
20. The apparatus according to claim 1 , further comprising:
an FET transistor configured (i) in series with a collector of the third transistor and (ii) to provide one or more of power down control and enhanced RF and thermal performance.
21. The apparatus according to claim 1 , further comprising:
an inductor (i) coupled to an emitter of the first stage and (ii) configured to provide low noise matching.