Power efficient multistage amplifier and design method
View Patent ↗A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier.
1. A multistage amplifier comprising:
a first amplifier stage having,
a first amplifier with a first amplifier output; and
a second amplifier stage connected with the first amplifier stage having,
a second amplifier with a second amplifier output, and
wherein the second amplifier is configured to drive the first amplifier within 5 dB of the first amplifier power added efficiency peak, and wherein each amplifier stage in said multistage amplifier is driven within 5 dB of that amplifier stage power added efficiency peak; and
wherein the second amplifier stage of the multistage amplifier further comprises a periphery for a second field effect transistor sized to obtain a substantially flat gain response for power levels within 3 dB of the first amplifier stage's power added efficiency peak.
2. The multistage amplifier of claim 1 wherein the first amplifier and the second amplifier each comprise a field effect transistor.
3. The multistage amplifier of claim 2 wherein the first amplifier and the second amplifier each comprise a high electron mobility field effect transistor.
4. The multistage amplifier of claim 1 wherein the first amplifier stage, the second amplifier stage or both are monolithic microwave integrated circuits.
5. The multistage amplifier of claim 3 wherein the first amplifier stage, the second amplifier stage or both have a gallium arsenide substrate.
6. The multistage amplifier of claim 1 wherein power added efficiency peak of the first and second amplifiers is 0 to 2 dB above a linear operating region.
7. The multistage amplifier of claim 1 further comprising a third amplifier stage connected with the second amplifier stage having;
a third amplifier with a third amplifier output, and
wherein the third amplifier is configured to drive the second amplifier within 5 dB of the second amplifier power added efficiency peak.
8. A method for designing a multistage amplifier comprising:
designing a final stake of the multistage amplifier to drive a load and operate within 5 dB of a final stage power added efficiency peak; and
designing a penultimate stage of the multistage amplifier to drive the final stage of the amplifier and operate within 5 dB of a penultimate stage power added efficiency peak, wherein designing the penultimate stage of the multistage amplifier further comprises sizing a periphery for a second field effect transistor and designing a second drive circuit to obtain a substantially flat gain response for power levels within 3 dB of the penultimate stage's power added efficiency peak.
9. The method of claim 8 further comprising designing an input circuit to drive a first stage of the multistage amplifier to obtain a flat gain response.
10. The method of claim 9 further comprising determining a frequency response of one or more stages of the multistage amplifier.
11. The method of claim 10 further comprising adjusting one or more design parameters to adjust the frequency response.
12. The method of claim 11 wherein a computer simulation tool is used to design one or more stages of the multistage amplifier.