IP Library Granted Patent US 7,498,880
Granted Patent B2
US 7,498,880 · App. 11/688,833 · Granted Mar 3, 2009

Class L amplifier

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Quick Facts
Patent No.
US 7,498,880
App. No.
11/688,833
Granted
Mar 3, 2009
Kind
B2
Abstract

A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. A bridged amplifier system using two Class L amplifiers to drive a load.

Claims (38)

1. An amplifier system comprising:

a first amplifier device coupled to receive an input signal and provide a first output signal; and

a first rail selector coupled to the first amplifier device, for coupling the first amplifier device to a first power rail and a second power rail in response to the output signal being lower than a first threshold, to couple the first amplifier device to a third power rail and the first power rail in response to the input signal being higher than the first threshold and lower than a second threshold, and to couple the first amplifier device to a fourth power rail and the first power rail in response to the input signal being higher than the second threshold;

a second amplifier device coupled to receive an input signal and provide a second output signal; and

a second rail selector coupled to the second amplifier device, for coupling the second amplifier device to a fifth power rail and a sixth power rail in response to the output signal being lower than a third threshold, to couple the second amplifier device to a seventh power rail and the fifth power rail in response to the input signal being higher than the third threshold and lower than a fourth threshold, and to couple the second amplifier device to an eighth power rail and the fifth power rail in response to the input signal being higher than the fourth threshold;

wherein the first rail selector comprises:

a third amplifier device coupled to receive the first and second output signals and, responsive thereto, to generate a first intermediate result signal;

a first comparator coupled to receive the first intermediate result signal and the third power rail and, responsive thereto, to generate a second intermediate result signal;

a second comparator coupled to receive the first intermediate result signal and the second power rail and, responsive thereto, to generate a third intermediate result signal;

a fourth amplifier device coupled to receive the first and second output signals and, responsive thereto, to generate a fourth intermediate result signal;

a third comparator coupled to receive the fourth intermediate result signal and the sixth power rail and, responsive thereto, to generate a fifth intermediate result signal;

a fourth comparator coupled to receive the fourth intermediate result signal and the seventh power rail and, responsive thereto, to generate a sixth intermediate result signal;

a NOR device coupled to receive the second, third, fifth, and sixth intermediate result signals and, responsive thereto, to generate a seventh result signal;

wherein,

the second intermediate result signal selects the fourth and first power rails for the first amplifier device and the sixth and fifth power rails for the second amplifier device,

the third intermediate result signal selects the third and first power rails for the first amplifier device and the sixth and fifth power rails for the second amplifier device,

the fifth intermediate result signal selects the second and first power rails for the first amplifier device and the seventh and fifth power rails for the second amplifier device,

the sixth intermediate result signal selects the second and first power rails for the first amplifier device and the eighth and fifth power rails for the second amplifier device, and

the seventh result signal selects the second and first power rails for the first amplifier device and the sixth and fifth power rails for the second amplifier device.

2. The amplifier system of claim 1 wherein:

the first input signal comprises a positive input signal;

the first amplifier device comprises a positive amplifier device;

the second input signal comprises a negative input signal; and

the second amplifier device comprises a negative amplifier device.

3. The amplifier system of claim 1 wherein:

the first rail selector is adapted to couple the first amplifier device to M possible rail combinations; and

the second rail selector is adapted to couple the second amplifier device to N possible rail combinations;

wherein M and N are positive integers and N is greater than one.

4. The amplifier system of claim 1 wherein:

the first, second, third, and fourth power rails comprise substantially equally spaced positive voltages.

5. The amplifier system of claim 1 wherein:

the first, second, third, and fourth power rails are configured such that the fourth is larger than the third, the third is larger than the second, and the second is larger than the first;

the fifth, sixth, seventh, and eighth power rails are configured such that the eighth is larger than the seventh, the seventh is larger than the sixth, and the sixth is larger than the fifth.

6. The amplifier system of claim 5 wherein:

the first and fifth power rails comprise ground.

7. The amplifier system of claim 5 wherein:

the first, second, third, and fourth power rails comprise substantially equally spaced voltages; and

the fifth, sixth, seventh, and eighth power rails comprise substantially equally spaced voltages.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2009
From: LEADIS TECHNOLOGY, INC.
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 022427/0461 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2007
From: DELANO, CARY L.
To: LEADIS TECHNOLOGY, INC.
Reel/Frame 019356/0134 →