POLYSILICON CONDUCTIVITY IMPROVEMENT IN A SALICIDE PROCESS TECHNOLOGY

1 . A method of forming a plurality of silicide layers on silicon-containing features of an electronic device, the method comprising:

depositing a first metal-containing layer over each of a first and a second silicon-containing feature;

performing a first annealing step to chemically react the first metal-containing layer with each of the first and second silicon-containing features forming a first and a second silicided region respectively;

forming a protective layer over the first and second silicided regions;

etching an opening in the protective layer to expose the first silicided region while continuing to mask the second silicided region;

depositing a second metal-containing layer over the first silicided region; and

performing a second annealing step to chemically react the second metal-containing layer with the first silicided region.

2 . The method of claim 1 wherein each of the first and second metal-containing layers is selected to be an elemental metallic material.

3 . The method of claim 1 wherein each of the first and second meal-containing layers is selected to be a compound metallic material.

4 . The method of claim 1 wherein the first silicon-containing feature is fabricated to form a transistor gate region.

5 . The method of claim 1 wherein the second silicon-containing feature is fabricated to form a transistor source/drain region.

6 . The method of claim 1 wherein at least one of the metal-containing layers is selected to include cobalt.

7 . The method of claim 1 wherein at least one of the metal-containing layers is selected to include nickel.

8 . The method of claim 1 wherein the protective layer is selected to be a dielectric material.

9 . A method of forming a plurality of silicide layers on silicon-containing features of an electronic device, the method comprising:

depositing a first metal-containing layer over each of a first and a second silicon-containing feature;

performing a first annealing step to chemically react the first metal-containing layer with each of the first and second silicon-containing features forming a first and a second silicided region respectively;

forming a dielectric protective layer over the first and second silicided regions;

forming a gap-filling dielectric layer substantially covering all features on the electronic device,

etching an opening in the dielectric protective layer to expose the first silicided region while continuing to mask the second silicided region;

depositing a second metal-containing layer over the first silicided region; and

performing a second annealing step to chemically react the second metal-containing layer with the first silicided region.

10 . The method of claim 9 further comprising:

planarizing the gap-filling dielectric layer such that it is substantially coplanar with an uppermost portion of the protective layer prior to etching the opening.

11 . The method of claim 9 wherein each of the first and second metal-containing layers is selected to be an elemental metallic material.

12 . The method of claim 9 wherein each of the first and second metal-containing layers is selected to be a compound metallic material.

13 . The method of claim 9 wherein the first silicon-containing feature is fabricated to form a transistor gate region.

14 . The method of claim 9 wherein the second silicon-containing feature is fabricated to form a transistor source/drain region.

15 . The method of claim 9 wherein at least one of the metal-containing layers is selected to include cobalt.

16 . The method of claim 9 wherein at least one of the metal-containing layers is selected to include nickel.

17 . An electronic device comprising:

a source and drain region, each region having an uppermost portion comprised of a first silicide, the first silicide being overlaid with a first dielectric layer; and

a gate region having an uppermost portion comprised of a second silicide, the second silicide being both thicker than the first silicide and having a lower resistivity than the first silicide, at least a portion of the second silicide being formed in an opening in the first dielectric layer.

18 . The electronic device of claim 17 further comprising a planarized second dielectric layer, the planarized second dielectric layer being substantially coplanar with an uppermost surface of a portion of the first dielectric layer.

19 . The electronic device of claim 17 wherein the first and second silicides are each comprised partially of cobalt.

20 . The electronic device of claim 17 wherein the first and second silicides are each comprised partially of nickel.