Thin film transistor array panel and manufacturing method thereof
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on an insulating substrate;
forming a gate insulating layer;
forming a semiconductor layer;
forming a data conductive layer including a data line and a drain electrode;
depositing a passivation layer;
forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion;
exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask;
forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and
forming a pixel electrode connected to the drain electrode through the first contact hole.
2. The method of claim 1 , wherein the photoresist further comprises a fourth portion disposed on an end portion of the data line, and the method further comprises forming a third contact hole exposing the end portion of the data line.
3. The method of claim 1 , wherein the exposure is performed by dry etching under a condition that etching ratios for the photoresist and the passivation layer are substantially the same.
4. The method of claim 1 , wherein the exposed portion of the gate line is thicker than the exposed portion of the passivation layer.
5. The method of claim 1 , wherein the formation of the first and second contact holes is performed by dry etching under a condition that etching ratios for the gate insulating layer and the passivation layer are substantially the same.
6. The method of claim 1 , wherein the gate line or the data line comprises a lower film of Cr, Mo or Mo alloy and an upper film of Al or Al alloy.
7. The method of claim 6 , further comprising:
removing the upper film before forming the pixel electrode.
8. The method of claim 1 , wherein the pixel electrode comprises IZO.
9. The method of claim 1 , wherein the data line and the semiconductor layer is formed using a single photoresist film.