Junction field effect transistor, integrated circuit for switching power supply, and switching power supply
A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.
1. A junction field effect transistor (JFET) comprising:
a semiconductor substrate of a first conductivity type;
a drain region of a second conductivity type in the semiconductor substrate;
a drain electrode electrically connected to the drain region;
a drift region of the second conductivity type in the semiconductor substrate;
a plurality of source regions of the second conductivity type in the semiconductor substrate;
a plurality of source electrodes each electrically connected to one of the source regions;
a gate region of the first conductivity in the semiconductor substrate in contact with the drift region and the source regions; and
a gate electrode electrically connected to the gate region,
wherein the drift region is between the drain region and the source regions, and
wherein the source electrodes are divided into at least a first source electrode group and a second source electrode group, which is electrically isolated from the first source electrode group,
wherein the source regions are formed circumferentially around the drift region, and
wherein the gate region is selectively formed in a surface layer of the semiconductor substrate to provide a plurality of recessed regions that extend radially outwardly, and each of the source regions is in one of the recessed regions.
2. The JFET according to claim 1 , wherein the source regions are equally spaced around the drift region.
3. The JFET according to claim 1 , wherein each of the source regions occupies a portion of the respective recessed region or an entire region of the respective recessed region.
4. The JFET according to claim 1 , further comprising a semiconductor region of the first conductivity type formed on the drift region and in contact with the drift region.