Current-triggered low turn-on voltage SCR
A system for protecting a high-speed input/output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input/output pad and a trigger input. The anode and the trigger input form a reverse-biased junction that, during normal operation of the integrated circuit, isolates the triggering mechanism from the input/output pad when power is applied to the integrated circuit.
1. A system for protecting an integrated circuit from an electrostatic discharge event at an input/output pad connected to the integrated circuit, the system comprising:
(a) a silicon controlled rectifier including:
(i) an anode operationally connected to the input/output pad, and
(ii) a trigger input separate from said anode, and
(b) a triggering mechanism operationally connected to said trigger input, said triggering mechanism including:
(i) an inverter configured to be powered by the electrostatic discharge event,
(ii) a resistor having a first terminal connected to said trigger input and a second terminal connected to an input of said inverter,
(iii) a capacitor having a first terminal connected to said second terminal of said resistor and a second, grounded terminal, and
(iv) a trigger transistor having a drain connected to said trigger input and also connected to a power supply line of the integrated circuit, a grounded source, and a gate connected to an output of said inverter;
wherein a time constant of said resistor and said capacitor is great enough that when an electrostatic discharge event occurs at the input/output pad while power is not applied to the integrated circuit, a voltage at said input of said inverter remains sufficiently low for a sufficiently long time for a voltage at said output of said inverter to be sufficiently high to cause said trigger transistor to conduct a trigger current operative to trigger said silicon control rectifier;
wherein, when power is applied to the integrated circuit, said capacitor is charged to a voltage sufficiently high to cause said voltage at said output of said inverter to be sufficiently low to cause said trigger transistor to be substantially non-conductive;
and wherein said anode and said trigger input form a reverse-biased diode operative to isolate said triggering mechanism from the input/output pad when power is applied to the integrated circuit.
2. The system of claim 1 , wherein said silicon controlled rectifier is operative to conduct at least a portion of a current caused by the electrostatic discharge event.
3. The system of claim 1 , wherein said silicon controlled rectifier is parasitic.
4. The system of claim 1 , wherein said anode includes a first p-type region; wherein said trigger input includes a first n-type region; wherein said silicon controlled rectifier further includes:
(iii) a cathode that includes a second n-type region, and
(iv) a second p-type region;
and wherein said first p-type region and said first n-type region form a first p-n junction, said first n-type region and said second p-type region form a second p-n junction, and said second p-type region and said second n-type region form a third p-n junction.
5. The system of claim 1 , wherein said triggering mechanism is operative, while power is not being applied to the integrated circuit, to trigger said silicon controlled rectifier to conduct at least a portion of a current caused by the electrostatic discharge event.
6. The system of claim 1 , wherein said triggering mechanism includes a transistor operative, when an electrostatic discharge event occurs, to conduct a triggering current so as to trigger said silicon controlled rectifier.
7. The system of claim 6 , wherein said transistor is a field effect transistor.
8. The system of claim 1 , wherein said silicon controlled rectifier has a trigger voltage of at most about 1.2V.