Field effect transistor having a stressed contact etch stop layer with reduced conformality
By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions.
1. A method, comprising:
depositing a stress-inducing layer having a first material composition above a gate electrode structure having a dielectric sidewall portion and drain and source regions of a field effect transistor by a non-conformal deposition process, said non-conformal deposition process producing said stress-inducing layer with a conformality ratio of approximately 70 percent or less with respect to said dielectric sidewall portion and a top surface of said gate electrode structure;
forming an interlayer dielectric material of a second material composition above said stress-inducing layer; and
forming contact openings in said interlayer dielectric material using said stress-inducing layer as an etch stop layer.
2. The method of claim 1 , further comprising removing a sidewall spacer from said gate electrode structure prior to depositing said stress-inducing layer.
3. The method of claim 2 , wherein removing said sidewall spacer comprises etching said sidewall spacer selectively to a liner separating said sidewall spacer from a surface of said drain and source regions and a sidewall of a gate electrode of said gate electrode structure.
4. The method of claim 3 , further comprising removing a portion of said liner formed above said surface of said drain and source regions, wherein said portion is located adjacent said gate electrode structure.
5. The method of claim 1 , wherein said stress-inducing layer has an intrinsic stress of approximately 1 Giga Pascal or higher.
6. The method of claim 1 , wherein said gate electrode structure comprises a gate electrode having a gate length of approximately 90 nm or less.
7. The method of claim 1 , wherein said conformality ratio of said stress-inducing layer is approximately 50 percent or less.
8. The method of claim 1 , wherein forming said interlayer dielectric material comprises performing at least one planarization process prior to forming said contact openings.
9. A method, comprising:
forming a first non-conformal stress-inducing layer above a first transistor, said first non-conformal stress-inducing layer having a first type of intrinsic stress; and
forming a second non-conformal stress-inducing layer above a second transistor, said second non-conformal stress-inducing layer having a second type of intrinsic stress other than said first type of intrinsic stress, said first and second stress-inducing layers having a conformality ratio of 70 percent or less.
10. The method of claim 9 , wherein a conformality ratio of said first and second stress-inducing layers is approximately 50 percent or less.
11. The method of claim 9 , wherein forming said first stress-inducing layer comprises forming a liner above said first and second transistors, depositing said first stress-inducing layer above said liner and removing a portion of said first stress-inducing layer located above said second transistor, using said liner as an etch stop layer.
12. The method of claim 11 , wherein said liner is formed by a non-conformal deposition process.
13. The method of claim 11 , further comprising planarizing a surface topography of said first stress-inducing layer prior to removing said portion thereof.
14. The method of claim 11 , wherein forming said second stress-inducing layer comprises depositing said second stress-inducing layer above said first and second transistors and removing a portion of said second stress-inducing layer that is located above said first transistor.
15. The method of claim 14 , further comprising forming contact openings in an interlayer dielectric material formed above said first and second stress-inducing layers by using a planarization process for planarizing a surface topography of said interlayer dielectric material prior to forming said contact openings.
16. A method, comprising:
forming a first transistor and a second transistor above a semiconductor layer formed above a semiconductor substrate;
forming a liner above said first transistor and said second transistor;
forming a first non-conformal stress-inducing layer above said liner, said first non-conformal stress-inducing layer having a first type of intrinsic stress and a first conformality ratio of 70 percent or less;
removing a portion of said first non-conformal stress-inducing layer located above said second transistor using said liner as an etch stop layer;
forming a second non-conformal stress-inducing layer above said second transistor, said second non-conformal stress-inducing layer having a second type of intrinsic stress other than said first type of intrinsic stress and a second conformality ratio of 70 percent or less.
17. The method of claim 16 , wherein said first conformality ratio of said first stress-inducing layer is approximately 50 percent or less.
18. The method of claim 16 , wherein said second conformality ratio of said second stress-inducing layer is approximately 50 percent or less.
19. The method of claim 16 , wherein said liner is formed by a non-conformal deposition process.
20. The method of claim 16 , further comprising planarizing a surface topography of said first stress-inducing layer prior to removing said portion thereof.
21. The method of claim 16 , wherein forming said second stress-inducing layer comprises depositing said second stress-inducing layer above said first and second transistors and removing a portion of said second stress-inducing layer that is located above said first transistor.
22. The method of claim 21 , further comprising forming contact openings in an interlayer dielectric material formed above said first and second stress-inducing layers by using a planarization process for planarizing a surface topography of said interlayer dielectric material prior to forming said contact openings.