Intra-macroblock video processing
View Patent ↗A system for processing sub-blocks of a macroblock of a video frame. In an example embodiment, the system includes a first module that is adapted to process each sub-block of the macroblock, wherein each sub-block is associated with a predetermined position in a first sequence. The processing of certain sub-blocks in the first sequence requires results of processing of one or more previously processed sub-blocks in the first sequence. A controller selectively enables the first module to process each sub-block of a second sequence that is altered from the first sequence so that the first module implements parallel or pipelined processing of certain sub-blocks of the macroblock. In a more specific embodiment each sub-block in the first sequence of sub-blocks is consecutively numbered 0-15 according to H.264 standards.
1. A system for processing sub-blocks of a macroblock, the system comprising:
a memory;
a processor operative to:
process each sub-block of the macroblock, wherein each sub-block is associated with a predetermined position in a first sequence, wherein the processing of certain sub-blocks in the first sequence requires results of processing of one or more previously processed sub-blocks in the first sequence, wherein the processing of one or more previously processed sub-blocks in the first sequence comprises the processor operative to form a prediction sub-block based on information pertaining to a current macroblock to be processed; and
selectively process each sub-block of the macroblock in a second sequence, wherein the second sequence is altered from the first sequence to enable the first module to process certain sub-blocks of the macroblock in parallel; and
a controller for controlling a demultiplexer to dispatch the sub-blocks of the macroblock and requisite processing information pertaining to the sub-blocks of the macroblock to the first sequence and the second sequence, wherein the sub-blocks are dispatched on successive clock ticks.
2. The system of claim 1 , wherein the processor is further operative to implement an intra prediction of pixels within each sub-block.
3. The system of claim 1 , further comprising first means for processing sub-blocks of certain pairs of sub-blocks in parallel.
4. The system of claim 1 , first means for processing sub-blocks of certain pairs of sub-blocks in a pipeline fashion.
5. The system of claim 3 , wherein the first means includes: a first engine and a second engine.
6. The system of claim 1 , wherein the demultiplexer is adapted to feed the requisite information pertaining to one or more sub-blocks to the processor in a desired sequence or in parallel in response to a predetermined control signal to enable processing of the one or more sub-blocks.
7. A method for processing a sub-block of a macroblock, the method comprising: receiving, at a processor, information to process a first sub-block, where the receiving information to process a first sub-block comprises receiving at least one previously processed sub-blocks in the first sub-block operative to form a prediction sub-block based on information pertaining to a current macroblock to be processed; receiving, at the processor, information to process a second sub-block; processing a first portion of the second sub-block simultaneously with a second portion of the first sub-block when information associated with one or more previously processed sub-blocks is simultaneously available for processing the first sub-block and the second sub-block; and
dispatching, by a multiplexer circuit, the first sub-block, the second sub-block and requisite processing information pertaining to the sub-blocks of the macroblock to the first sequence and the second sequence, wherein the sub-blocks are dispatched on successive clock ticks.
8. An apparatus for facilitating processing a macroblock, the apparatus comprising:
a processor operative to selectively stagger the delivery of information pertaining to a first sequence of sub-blocks and a second sequence of sub-blocks to the processor so that one or more sub-blocks of the first sequence or the second sequence that are required for processing certain sub-blocks of the first sequence and second sequence in parallel, are available to the processor before the processor processes the certain sub-blocks, where the information pertaining to the first sequence of sub-blocks comprises at least one previously processed sub-block in the first sequence of sub-blocks operative to form a prediction sub-block based on information pertaining to a current macroblock to be processed; and
a controller circuit for controlling a demultiplexer to dispatch sub-blocks of the macroblock and the information pertaining to the sub-blocks of the macroblock to the first sequence and the second sequence, wherein the sub-blocks are dispatched on successive clock ticks.
9. The apparatus of claim 8 , wherein the certain sub-blocks include a certain pair of sub-blocks.
10. The apparatus of claim 8 , further comprising an output operative to selectively deliver, from the processor, certain processed pairs of sub-blocks, wherein the processed pairs were processed in parallel by the processor.
11. A system for processing a macroblock, the system comprising:
a memory;
a processor operative to:
process a sub-block; and
selectively enable the processor to begin processing a first sub-block and enable the processor to begin processing a second sub-block without waiting for the processor to complete processing of the first sub-block, when information is available to process the second sub-block, wherein the information available to process the second sub-block comprises a prediction sub-block based on the second sub-block; and
a controller for controlling a demultiplexer to dispatch sub-blocks of the macroblock and requisite processing information pertaining to the sub-blocks of the macroblock to the first sequence and the second sequence, wherein the sub-blocks are dispatched on successive clock ticks.
12. The system of claim 1 , wherein the prediction sub-block is formed based on neighbor sub-block information and processed pixel data representing reconstructed pixels pertaining to requisite sub-blocks of the current macroblock.
13. The system of claim 1 , wherein the neighbor sub-block information include information regarding top, top right and left sub-blocks in the macroblock.
14. The system of claim 13 , wherein the processor is further operative to:
transform the residual macroblock from time domain to frequency domain to form a transformed macroblock;
quantize and then dequantize the transformed macroblock; and
transform the dequantized transformed macroblock from the frequency domain to time domain to form a resulting residual macroblock.
15. The system of claim 14 , wherein the processor is further operative to add the resulting residual macroblock to the predicted sub-block to form a reconstructed macroblock.
16. The system of claim 14 , wherein the processor is further operative to track a bit production rate wherein bit production is a number of bits processed during quantization of the transformed macroblock.
17. The system of claim 14 , wherein the sub-blocks and the requisite processing information pertaining to the sub-blocks are dispatched to the first sequence and the second sequence based on at least one of the following: a picture complexity, current bit buffer levels and the bit production rate from the previous sub-blocks.
18. The system of claim 14 , wherein the processor is further operative to determine a sum absolute difference (SAD) value, wherein the SAD value represent a measure of quality, efficiency and accuracy of the prediction sub-block.
19. The system of claim 18 , wherein the accuracy of the prediction sub-block is a measure of how closely the predicted sub-block matches with corresponding original sub-block in unprocessed macroblock.
20. The system of claim 1 , wherein the processor is further operative to subtract the predicted sub-block from the corresponding macroblock to form a residual macroblock.