Method and apparatus for exploiting thread-level parallelism
According to one example embodiment, there is disclosed herein uses partial recurrence relaxation for parallelizing DOACROSS loops on multi-core computer architectures. By one example definition, a DOACROSS may be a loop that allows successive iterations executing by overlapping; that is, all iterations must impose a partial execution order. According to one embodiment, the inventive subject matter may be used to transform the dependence structure of a given loop with recurrences for maximal degree of thread-level parallelism (TLP), where the threads can be mapped on to either different logical processors (in a hyperthreaded processor) or can be mapped onto different physical cores (or processors) in a multi-core processor.
1. A method comprising:
modifying, using one or more processors, computer code by relaxing the dependence between iterations of at least one loop in the code, wherein relaxing the dependence between iterations of at least one loop includes removing dependencies between consecutive iterations of the at least one loop; and
wherein the modification in the code is based on the number of physical or logical cores in the processor and the impact of further relaxation on the increase in the amount of computation or memory operations required to execute the further relaxed dependencies.
2. A method comprising:
modifying, using one or more processors, computer code by relaxing the dependence between iterations of at least one loop in the code, wherein the modification in the code is based on the number of physical or logical cores in the processor and the impact of further relaxation on the increase in the amount of computation or memory operations required to execute the further relaxed dependencies;
building a data dependence graph of an iteration of at least one of the loops;
computing the minimum dependence distance to determine a recurrence;
computing a relaxation factor for the recurrence;
updating the dependence graph of the loop based on the relaxation factor;
inserting a post-wait synchronization or barrier synchronization in a transformed loop; and
dynamically mapping the iterations of the transformed loop on to an idle thread.
3. A method according to claim 2 wherein the method is carried out by a computer program stored on a machine readable medium.
4. A method according to claim 2 further wherein the dependence structure of at least one of the loops is transformed with recurrences for maximal degree of thread-level parallelism.
5. A method according to claim 4 wherein the threads are mapped on to either different logical processors or can be mapped onto different physical cores.
6. A method according to claim 2 further wherein at least one loop is parallelized.
7. A method according to claim 2 further wherein a transformed loop enables exploitation of nested loop-level parallelism.
8. A system comprising:
a computing system including at least one processor with one or more physical cores;
computer code including a loop, wherein the computer code is executed on the computing system; and
a component configured to:
optimize the computer code by relaxing the dependence between iterations of the loop based on the number of physical cores in the processor and the impact of further relaxation on the increase in the amount of computation and memory operations required to execute the further relaxed dependencies: and
wherein relaxing the dependence between iterations includes operations to:
build a data dependence graph of an iteration of the loop;
compute the minimum dependence distance to determine a recurrence;
compute a relaxation factor for the recurrence;
update the dependence graph of the loop based on the relaxation factor;
insert a post-wait synchronization or barrier synchronization in a transformed loop; and
dynamically map the iterations of the transformed loop on to an idle thread.
9. A system according to claim 8 wherein at least one activity is performed dynamically.
10. A system according to claim 8 further wherein the dependence structure of at least one of the loops is transformed with recurrences for maximal degree of thread-level parallelism.
11. A system according to claim 10 wherein threads are mapped on to either different logical processors or can be mapped onto different physical cores.
12. A system according to claim 8 further wherein at least one loop is parallelized and executed by the system at least partially in parallel.
13. A system according to claim 8 further wherein a transformed loop enables exploitation of nested loop-level parallelism.
14. A non-transitory machine-accessible medium having stored thereon instructions, wherein the instructions, when accessed, result in a machine performing method of claim 1 operations comprising:
modifying, using one or more processors, computer code by relaxing the dependence between iterations of at least one loop in the code, wherein the modification in the code is based on the number of physical or logical cores in the processor and the impact of further relaxation on the increase in the amount of computation or memory operations required to execute the further relaxed dependencies;
building a data dependence graph of an iteration of at least one of the loops;
computing the minimum dependence distance to determine a recurrence;
computing a relaxation factor for the recurrence;
updating the dependence graph of the loop based on the relaxation factor;
inserting a post-wait synchronization or barrier synchronization in a transformed loop; and
dynamically mapping the iterations of the transformed loop on to an idle thread.
15. A system according to claim 8 wherein the component is a compiler program launched from a non-transitory computer-readable medium.