IP Library Granted Patent US 7,754,510
Granted Patent B2
US 7,754,510 · App. 11/695,131 · Granted Jul 13, 2010

Phase-separated dielectric structure fabrication process

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Quick Facts
Patent No.
US 7,754,510
App. No.
11/695,131
Granted
Jul 13, 2010
Kind
B2
Abstract

A process for fabricating an electronic device including: depositing a layer comprising a semiconductor; liquid depositing a dielectric composition comprising a lower-k dielectric material, a higher-k dielectric material, and a liquid, wherein the lower-k dielectric material and the higher-k dielectric material are not phase separated prior to the liquid depositing; and causing phase separation of the lower-k dielectric material and the higher-k dielectric material to form a phase-separated dielectric structure wherein the lower-k dielectric material is in a higher concentration than the higher-k dielectric material in a region of the dielectric structure closest to the layer comprising the semiconductor, wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation.

Claims (31)

1. A process for fabricating an electronic device comprising:

depositing a layer comprising a semiconductor;

liquid depositing a dielectric composition comprising a lower-k dielectric polymer, a higher-k dielectric polymer, and a liquid, wherein the lower-k dielectric polymer and the higher-k dielectric polymer are not phase separated prior to the liquid depositing; and

causing phase separation of the lower-k dielectric polymer and the higher-k dielectric polymer to form a phase-separated dielectric structure wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the layer comprising the semiconductor wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation.

2. The process of claim 1 , wherein the liquid depositing is accomplished in a single step.

3. The process of claim 1 , wherein the phase separation is caused by thermal annealing.

4. The process of claim 1 , wherein the lower-k dielectric polymer is at a concentration ranging from about 60% to 100% and the higher-k dielectric polymer is at a concentration ranging from about 40% to 0% of the total weight of the lower-k and the higher-k dielectric polymers in the region of the dielectric structure closest to the layer comprising the semiconductor.

5. The process of claim 1 , wherein the lower-k dielectric polymer is at a concentration ranging from about 80% to 100% and the higher-k dielectric polymer is at a concentration ranging from about 20% to 0% of the total weight of the lower-k and the higher-k dielectric polymers in the region of the dielectric structure closest to the layer comprising the semiconductor.

6. The process of claim 1 , wherein the lower-k dielectric polymer has a dielectric constant of less than 4.0.

7. The process of claim 1 , wherein the higher-k dielectric polymer has a dielectric constant of 4.0 or more.

8. The process of claim 1 , wherein the dielectric composition is non-photoimageable.

9. A process for fabricating an electronic device comprising:

depositing a layer comprising a semiconductor;

liquid depositing in a single step a dielectric composition comprising a lower-k dielectric polymer, a higher-k dielectric polymer, and a liquid, wherein the lower-k dielectric polymer and the higher-k dielectric polymer are not phase separated prior to the liquid depositing; and

causing phase separation of the lower-k dielectric polymer and the higher-k dielectric polymer to form a phase-separated dielectric structure wherein the lower-k dielectric polymer is at a concentration ranging from about 60% to 100% and the higher-k dielectric polymer is at a concentration ranging from about 40% to 0% of the total weight of the lower-k and the higher-k dielectric polymers in a region of the dielectric structure closest to the layer comprising the semiconductor

wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation.

10. The process of claim 9 , wherein the phase separation is caused by thermal annealing.

11. The process of claim 9 , wherein the lower-k dielectric polymer is at a concentration ranging from about 80% to 100% and the higher-k dielectric polymer is at a concentration ranging from about 20% to 0% of the total weight of the lower-k and the higher-k dielectric polymers in the region of the dielectric structure closest to the layer comprising the semiconductor.

12. The process of claim 9 , wherein the lower-k dielectric polymer has a dielectric constant of less than 4.0.

13. The process of claim 9 , wherein the higher-k dielectric polymer has a dielectric constant of 4.0 or more.

14. A process for fabricating a thin film transistor comprising:

depositing a layer comprising a semiconductor;

liquid depositing a dielectric composition comprising a lower-k dielectric polymer, a higher-k dielectric polymer, and a liquid, wherein the lower-k dielectric polymer and the higher-k dielectric polymer are dissolved in the liquid; and

causing phase separation of the lower-k dielectric polymer and the higher-k dielectric polymer to form a phase-separated gate dielectric comprising a lower-k dielectric polymer-majority/higher-k dielectric polymer-minority first phase and a higher-k dielectric polymer-majority/lower-k dielectric polymer-minority second phase, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the layer comprising the semiconductor

wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation;

wherein the lower-k dielectric polymer has a dielectric constant of less than 4.0; and

wherein the higher-k dielectric polymer has a dielectric constant of 4.0 or more.

15. The process of claim 14 , wherein the lower-k dielectric polymer is at a concentration ranging from about 60% to 100% and the higher-k dielectric polymer is at a concentration ranging from about 40% to 0% of the total weight of the lower-k and the higher-k dielectric polymers in the region of the dielectric structure closest to the layer comprising the semiconductor.

16. The process of claim 14 , wherein the lower-k dielectric polymer is at a concentration ranging from about 80% to 100% and the higher-k dielectric polymer is at a concentration ranging from about 20% to 0% of the total weight of the lower-k and the higher-k dielectric polymers in the region of the dielectric structure closest to the layer comprising the semiconductor.

17. The process of claim 14 , wherein the lower-k dielectric polymer has a dielectric constant of less than about 3.5.

18. The process of claim 14 , wherein the lower-k dielectric polymer comprises a polysilsesquioxane.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073842/0479 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
RELEASE OF SECURITY INTEREST IN PATENTS AT R/F 062740/0214 Recorded May 18, 2023
From: CITIBANK, N.A., AS AGENT
To: XEROX CORPORATION
Reel/Frame 063694/0122 →
SECURITY INTEREST Recorded Nov 10, 2022
From: XEROX CORPORATION
To: CITIBANK, N.A., AS AGENT
Reel/Frame 062740/0214 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2007
From: WU, YILIANG , ,; MAHABADI, HADI K, ,; ONG, BENG S, ,; SMITH, PAUL F, ,
To: XEROX CORPORATION
Reel/Frame 019195/0342 →