Thin film transistor array panel and method of manufacturing the same
A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.
1. A method of manufacturing a thin film transistor (TFT) array panel on a substrate, comprising:
forming a plurality of gate lines on the substrate;
forming a plurality of gate electrodes by a photolithography process;
forming a gate insulating layer on the substrate and the gate electrodes;
forming a semiconductor layer on the gate insulating layer;
forming an ohmic contact layer on the semiconductor layer;
forming a desired active area by a photolithography process;
forming a conductive layer on the gate insulating layer and the ohmic contact layer;
forming a plurality of drain electrodes, data lines having a plurality of source electrodes, and a plurality of conductive patterns, wherein the drain electrodes extend parallel with and adjacent to the data lines and are directly connected to the conductive patterns, and wherein the conductive patterns overlap an adjacent gate line;
forming an insulating layer on all of the data lines, the drain electrodes, the source electrodes, the gate insulating layer, and the conductive patterns, the insulating layer having a contact hole, and
forming a plurality of pixel electrodes on the insulating layer, the pixel electrodes being electrically connected to the conductive patterns through the contact hole.
2. The method of claim 1 , wherein the insulating layer is made of an organic material.
3. The method of claim 1 , wherein the pixel electrodes cover both the drain electrodes and the data lines.
4. A method of manufacturing a thin film transistor (TFT) array panel on a substrate, comprising:
forming a plurality of gate lines on the substrate;
forming a plurality of gate electrodes patterned by a photolithography process using a mask;
forming a gate insulating layer on the substrate and the gate electrodes;
forming a semiconductor layer on the gate insulating layer;
forming an ohmic contact layer on the semiconductor layer;
forming a conductive layer on the ohmic contact layer;
forming a plurality of drain electrodes, data lines having a plurality of source electrodes, and a plurality of conductive patterns, wherein the drain electrodes extend parallel with and adjacent to the data lines and are directly connected to the conductive patterns, and wherein the conductive patterns overlap an adjacent gate line;
forming an insulating layer on all of the data lines, the drain electrodes, the source electrodes, the gate insulating layer and the conductive patterns, the insulating layer having a contact hole, and
forming a plurality of pixel electrodes on the insulating layer, the pixel electrodes being electrically connected to the conductive patterns through the contact hole.
5. The method of claim 4 , wherein the conductive patterns have a three-layered structure.
6. The method of claim 5 , wherein the three-layered structure is layered in the order of the semiconductor layer, the ohmic contact layer, and the conductive pattern.
7. The method of claim 4 , wherein the drain electrodes have a three-layered structure.
8. The method of claim 7 , wherein the three-layered structure is layered in the order of the semiconductor layer, the ohmic contact layer, and the conductive pattern.
9. The method of claim 4 , wherein the insulating layer is made of an organic material.
10. The method of claim 4 , wherein the pixel electrodes cover an adjacent data line.
11. The method of claim 10 , wherein the pixel electrodes cover the drain electrodes.